#define HARDWARE_GLOBALS
#include "config.h"
#include "../include/cfg_net.h"
#include 	"LPC23XX_ADD_R.h"

union  REC_BUFF_UNION	REC_BUFF[MAX_REC_BUFF];
/* EMAC MODULE ID	*/
#define PHILIPS_EMAC_MODULE_ID	((0x3902 << 16) | 0x2000)

uint32      tempreg1,tempreg;
uint16 PHYREG[80];
uint16 PHYID;
uint8  LINKSTATUS;
volatile uint32 RXOverrunCount = 0;
volatile uint32 RXErrorCount = 0;

volatile uint32 TXUnderrunCount = 0;
volatile uint32 TXErrorCount = 0;
volatile uint32 RxFinishedCount = 0;
volatile uint32 TxFinishedCount = 0;
volatile uint32 TxDoneCount = 0;
volatile uint32 RxDoneCount = 0;

volatile uint32 CurrentRxPtr = EMAC_RX_BUFFER_ADDR;
volatile uint32 ReceiveLength = 0;
volatile uint32 PacketReceived = FALSE;

uint16 EthernetPHYRead(uint8 paddr,uint8 raddr)
{
	uint16 temp16;
	
	rMCMD = 1;					//enable read 
	rMADR = ((paddr&0X1F) <<8 ) + (raddr&0X1F);
	while(rMIND & 0X01);
	rMCMD = 0;
	temp16 = rMRDD;
	return temp16;	
}
/******************************************************************************
** Function name:		EMAC_TxEnable/EMAC_TxDisable
**
** Descriptions:		EMAC TX API modules
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void EMAC_TxEnable( void )
{
    MAC_COMMAND |= 0x02;
    return;
}

void EMAC_TxDisable( void )
{
    MAC_COMMAND &= ~0x02;
    return;
}

/******************************************************************************
** Function name:		EMAC_RxEnable/EMAC_RxDisable
**
** Descriptions:		EMAC RX API modules
**
** parameters:			None
** Returned value:		None
** 
******************************************************************************/
void EMAC_RxEnable( void )
{
    MAC_COMMAND |= 0x01;
    MAC_MAC1 |= 0x01;
    return;    
}

void EMAC_RxDisable( void )
{
    MAC_COMMAND &= ~0x01;
    MAC_MAC1 &= ~0x01;
    return;
}
void WritePHY( uint32 PHYReg, uint32 PHYData )
{
    MAC_MCMD = 0x0000;			/* write command */
    MAC_MADR = 0X0300 | PHYReg;	/* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */
    MAC_MWTD = PHYData;
    while ( MAC_MIND != 0 );
    return;
}

void Write_PHY (uint16 phyadd,int PhyReg, int Value)
{
  unsigned int tout;

  MAC_MADR = (phyadd<<8) | PhyReg;
  MAC_MWTD = Value;

  /* Wait utill operation completed */
  tout = 0;
  for (tout = 0; tout < 50000; tout++) {
    if ((MAC_MIND & 1) == 0) {
      break;
    }
  }
}
/*****************************************************************************
** Function name:		ReadPHY
**
** Descriptions:		Read data from the PHY port
**
** parameters:			PHY register
** Returned value:		PHY data
** 
*****************************************************************************/

uint32 ReadPHY( uint16 phyadd,uint32 PHYReg )
{
    uint32 i32;
    MAC_MCMD = 0x0001;			/* read command */
    i32 = (phyadd<<8) | PHYReg;	/* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */ 
    MAC_MADR = i32;
    while ( MAC_MIND != 0 );
    MAC_MCMD = 0x0000;
    return( MAC_MRDD );
}
unsigned short Read_PHY ( uint16 phyadd ,unsigned char PhyReg) 
{
  unsigned int tout;

  MAC_MADR = (phyadd<<8) | PhyReg;
  MAC_MCMD = 1;

  /* Wait until operation completed */
  for (tout = 0; tout < 50000; tout++) {
    if ((MAC_MIND & 1) == 0) {
      break;
    }
  }
  MAC_MCMD = 0;
  return (MAC_MRDD);
}

/*****************************************************************************
** Function name:		EMACTxDesciptorInit
**
** Descriptions:		initialize EMAC TX descriptor table
**
** parameters:			None
** Returned value:		None
** 
*****************************************************************************/
void EMACTxDescriptorInit( void )
{
    uint32 i;
    uint32 *tx_desc_addr, *tx_status_addr;
   
    /*-----------------------------------------------------------------------------      
     * setup the Tx status,descriptor registers -- 
     * Note, the actual tx packet data is loaded into the ahb2_sram16k memory as part
     * of the simulation
     *----------------------------------------------------------------------------*/ 
    MAC_TXDESCRIPTOR = TX_DESCRIPTOR_ADDR;	/* Base addr of tx descriptor array */
    MAC_TXSTATUS = TX_STATUS_ADDR;		/* Base addr of tx status */
    MAC_TXDESCRIPTORNUM = EMAC_TX_DESCRIPTOR_COUNT - 1;	/* number of tx descriptors, 16 */

    for ( i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++ )
    {
		tx_desc_addr = (uint32 *)(TX_DESCRIPTOR_ADDR + i * 8);	/* two words at a time, packet and control */
		*tx_desc_addr = (uint32)(EMAC_TX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE);
		*(tx_desc_addr+1) = (uint32)(EMAC_TX_DESC_INT | (EMAC_BLOCK_SIZE - 1));	/* set size only */
    }
    
    for ( i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++ )
    {
		tx_status_addr = (uint32 *)(TX_STATUS_ADDR + i * 4);	/* TX status, one word only, status info. */
		*tx_status_addr = (uint32)0;		/* initially, set status info to 0 */
    }
    MAC_TXPRODUCEINDEX = 0x0;	/* TX descriptors point to zero */
    return;
}

/*****************************************************************************
** Function name:		EMACRxDesciptorInit
**
** Descriptions:		initialize EMAC RX descriptor table
**
** parameters:			None
** Returned value:		None
** 
*****************************************************************************/
void EMACRxDescriptorInit( void )
{
    uint32 i;
    uint32 *rx_desc_addr, *rx_status_addr;
   
    /*-----------------------------------------------------------------------------      
     * setup the Rx status,descriptor registers -- 
     * Note, the actual rx packet data is loaded into the ahb2_sram16k memory as part
     * of the simulation
     *----------------------------------------------------------------------------*/ 
    MAC_RXDESCRIPTOR = RX_DESCRIPTOR_ADDR;	/* Base addr of rx descriptor array */
    MAC_RXSTATUS = RX_STATUS_ADDR;			/* Base addr of rx status */
    MAC_RXDESCRIPTORNUM = EMAC_RX_DESCRIPTOR_COUNT - 1;	/* number of rx descriptors, 16 */

    for ( i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++ )
    {
		/* two words at a time, packet and control */
		rx_desc_addr = (uint32 *)(RX_DESCRIPTOR_ADDR + i * 8);
		*rx_desc_addr = (uint32)(EMAC_RX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE);
		*(rx_desc_addr+1) = (uint32)(EMAC_RX_DESC_INT | (EMAC_BLOCK_SIZE - 1));	/* set size only */    
    }
 
    for ( i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++ )
    {
		/* RX status, two words, status info. and status hash CRC. */
		rx_status_addr = (uint32 *)(RX_STATUS_ADDR + i * 8);	
		*rx_status_addr = (uint32)0;	/* initially, set both status info and hash CRC to 0 */
		*(rx_status_addr+1) = (uint32)0; 
    }
    MAC_RXCONSUMEINDEX = 0x0;	/* RX descriptor points to zero */
    return;
}

/**********************************************************************
**函數(shù)原型：    void 	SetMacID()
**入口參數(shù):		*mac_ptr
**出口參數(shù):		無
**返 回 值：	無            
**說    明：	設置芯片物理地址,物理地址已經(jīng)存儲在程序空間內(nèi) 
************************************************************************/
void SetMacID(uint8 * mac_ptr)   
{

	MAC_SA0 = mac_ptr[0]*256+mac_ptr[1];
    MAC_SA1 = mac_ptr[2]*256+mac_ptr[3];
    MAC_SA2 = mac_ptr[4]*256+mac_ptr[5];
	//把MAC地址寫入MY——MAC——ID中
	
}
uint32 EMACSend( uint32 *EMACBuf, uint32 length )
{
    uint32 *tx_desc_addr;
    uint32 TxProduceIndex;
    uint32 TxConsumeIndex;
    uint32 i, templen;

    TxProduceIndex = MAC_TXPRODUCEINDEX;
    TxConsumeIndex = MAC_TXCONSUMEINDEX;

    if ( TxConsumeIndex != TxProduceIndex )
    {
		return ( FALSE );
    }

    if ( TxProduceIndex == EMAC_TX_DESCRIPTOR_COUNT )
    {
		/* reach the limit, that probably should never happen */