?? dsp28_ecan.h
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//
// TMDX ALPHA RELEASE
//
//###########################################################################
//
// FILE: DSP28_ECan.h
//
// TITLE: DSP28 Device eCAN Register Definitions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
// 0.56| 20 May 2002 | L.H. | No change
// 0.57| 27 May 2002 | L.H. | No change
//###########################################################################
#ifndef DSP28_ECAN_H
#define DSP28_ECAN_H
/* --------------------------------------------------- */
/* eCAN Control & Status Registers */
/* ----------------------------------------------------*/
/* eCAN Mailbox enable register (CANME) bit definitions */
struct CANME_BITS { // bit description
Uint16 ME0:1; // 0 Enable Mailbox 0
Uint16 ME1:1; // 1 Enable Mailbox 1
Uint16 ME2:1; // 2 Enable Mailbox 2
Uint16 ME3:1; // 3 Enable Mailbox 3
Uint16 ME4:1; // 4 Enable Mailbox 4
Uint16 ME5:1; // 5 Enable Mailbox 5
Uint16 ME6:1; // 6 Enable Mailbox 6
Uint16 ME7:1; // 7 Enable Mailbox 7
Uint16 ME8:1; // 8 Enable Mailbox 8
Uint16 ME9:1; // 9 Enable Mailbox 9
Uint16 ME10:1; // 10 Enable Mailbox 10
Uint16 ME11:1; // 11 Enable Mailbox 11
Uint16 ME12:1; // 12 Enable Mailbox 12
Uint16 ME13:1; // 13 Enable Mailbox 13
Uint16 ME14:1; // 14 Enable Mailbox 14
Uint16 ME15:1; // 15 Enable Mailbox 15
Uint16 ME16:1; // 16 Enable Mailbox 16
Uint16 ME17:1; // 17 Enable Mailbox 17
Uint16 ME18:1; // 18 Enable Mailbox 18
Uint16 ME19:1; // 19 Enable Mailbox 19
Uint16 ME20:1; // 20 Enable Mailbox 20
Uint16 ME21:1; // 21 Enable Mailbox 21
Uint16 ME22:1; // 22 Enable Mailbox 22
Uint16 ME23:1; // 23 Enable Mailbox 23
Uint16 ME24:1; // 24 Enable Mailbox 24
Uint16 ME25:1; // 25 Enable Mailbox 25
Uint16 ME26:1; // 26 Enable Mailbox 26
Uint16 ME27:1; // 27 Enable Mailbox 27
Uint16 ME28:1; // 28 Enable Mailbox 28
Uint16 ME29:1; // 29 Enable Mailbox 29
Uint16 ME30:1; // 30 Enable Mailbox 30
Uint16 ME31:1; // 31 Enable Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANME_REG {
Uint32 all;
struct CANME_BITS bit;
};
/* eCAN Mailbox direction register (CANMD) bit definitions */
struct CANMD_BITS { // bit description
Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx
Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx
Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx
Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx
Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx
Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx
Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx
Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx
Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx
Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx
Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx
Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx
Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx
Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx
Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx
Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx
Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx
Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx
Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx
Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx
Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx
Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx
Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx
Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx
Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx
Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx
Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx
Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx
Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx
Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx
Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx
Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx
};
/* Allow access to the bit fields or entire register */
union CANMD_REG {
Uint32 all;
struct CANMD_BITS bit;
};
/* eCAN Transmit Request Set register (CANTRS) bit definitions */
struct CANTRS_BITS { // bit description
Uint16 TRS0:1; // 0 TRS for Mailbox 0
Uint16 TRS1:1; // 1 TRS for Mailbox 1
Uint16 TRS2:1; // 2 TRS for Mailbox 2
Uint16 TRS3:1; // 3 TRS for Mailbox 3
Uint16 TRS4:1; // 4 TRS for Mailbox 4
Uint16 TRS5:1; // 5 TRS for Mailbox 5
Uint16 TRS6:1; // 6 TRS for Mailbox 6
Uint16 TRS7:1; // 7 TRS for Mailbox 7
Uint16 TRS8:1; // 8 TRS for Mailbox 8
Uint16 TRS9:1; // 9 TRS for Mailbox 9
Uint16 TRS10:1; // 10 TRS for Mailbox 10
Uint16 TRS11:1; // 11 TRS for Mailbox 11
Uint16 TRS12:1; // 12 TRS for Mailbox 12
Uint16 TRS13:1; // 13 TRS for Mailbox 13
Uint16 TRS14:1; // 14 TRS for Mailbox 14
Uint16 TRS15:1; // 15 TRS for Mailbox 15
Uint16 TRS16:1; // 16 TRS for Mailbox 16
Uint16 TRS17:1; // 17 TRS for Mailbox 17
Uint16 TRS18:1; // 18 TRS for Mailbox 18
Uint16 TRS19:1; // 19 TRS for Mailbox 19
Uint16 TRS20:1; // 20 TRS for Mailbox 20
Uint16 TRS21:1; // 21 TRS for Mailbox 21
Uint16 TRS22:1; // 22 TRS for Mailbox 22
Uint16 TRS23:1; // 23 TRS for Mailbox 23
Uint16 TRS24:1; // 24 TRS for Mailbox 24
Uint16 TRS25:1; // 25 TRS for Mailbox 25
Uint16 TRS26:1; // 26 TRS for Mailbox 26
Uint16 TRS27:1; // 27 TRS for Mailbox 27
Uint16 TRS28:1; // 28 TRS for Mailbox 28
Uint16 TRS29:1; // 29 TRS for Mailbox 29
Uint16 TRS30:1; // 30 TRS for Mailbox 30
Uint16 TRS31:1; // 31 TRS for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRS_REG {
Uint32 all;
struct CANTRS_BITS bit;
};
/* eCAN Transmit Request Reset register (CANTRR) bit definitions */
struct CANTRR_BITS { // bit description
Uint16 TRR0:1; // 0 TRR for Mailbox 0
Uint16 TRR1:1; // 1 TRR for Mailbox 1
Uint16 TRR2:1; // 2 TRR for Mailbox 2
Uint16 TRR3:1; // 3 TRR for Mailbox 3
Uint16 TRR4:1; // 4 TRR for Mailbox 4
Uint16 TRR5:1; // 5 TRR for Mailbox 5
Uint16 TRR6:1; // 6 TRR for Mailbox 6
Uint16 TRR7:1; // 7 TRR for Mailbox 7
Uint16 TRR8:1; // 8 TRR for Mailbox 8
Uint16 TRR9:1; // 9 TRR for Mailbox 9
Uint16 TRR10:1; // 10 TRR for Mailbox 10
Uint16 TRR11:1; // 11 TRR for Mailbox 11
Uint16 TRR12:1; // 12 TRR for Mailbox 12
Uint16 TRR13:1; // 13 TRR for Mailbox 13
Uint16 TRR14:1; // 14 TRR for Mailbox 14
Uint16 TRR15:1; // 15 TRR for Mailbox 15
Uint16 TRR16:1; // 16 TRR for Mailbox 16
Uint16 TRR17:1; // 17 TRR for Mailbox 17
Uint16 TRR18:1; // 18 TRR for Mailbox 18
Uint16 TRR19:1; // 19 TRR for Mailbox 19
Uint16 TRR20:1; // 20 TRR for Mailbox 20
Uint16 TRR21:1; // 21 TRR for Mailbox 21
Uint16 TRR22:1; // 22 TRR for Mailbox 22
Uint16 TRR23:1; // 23 TRR for Mailbox 23
Uint16 TRR24:1; // 24 TRR for Mailbox 24
Uint16 TRR25:1; // 25 TRR for Mailbox 25
Uint16 TRR26:1; // 26 TRR for Mailbox 26
Uint16 TRR27:1; // 27 TRR for Mailbox 27
Uint16 TRR28:1; // 28 TRR for Mailbox 28
Uint16 TRR29:1; // 29 TRR for Mailbox 29
Uint16 TRR30:1; // 30 TRR for Mailbox 30
Uint16 TRR31:1; // 31 TRR for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRR_REG {
Uint32 all;
struct CANTRR_BITS bit;
};
/* eCAN Transmit Acknowledge register (CANTA) bit definitions */
struct CANTA_BITS { // bit description
Uint16 TA0:1; // 0 TA for Mailbox 0
Uint16 TA1:1; // 1 TA for Mailbox 1
Uint16 TA2:1; // 2 TA for Mailbox 2
Uint16 TA3:1; // 3 TA for Mailbox 3
Uint16 TA4:1; // 4 TA for Mailbox 4
Uint16 TA5:1; // 5 TA for Mailbox 5
Uint16 TA6:1; // 6 TA for Mailbox 6
Uint16 TA7:1; // 7 TA for Mailbox 7
Uint16 TA8:1; // 8 TA for Mailbox 8
Uint16 TA9:1; // 9 TA for Mailbox 9
Uint16 TA10:1; // 10 TA for Mailbox 10
Uint16 TA11:1; // 11 TA for Mailbox 11
Uint16 TA12:1; // 12 TA for Mailbox 12
Uint16 TA13:1; // 13 TA for Mailbox 13
Uint16 TA14:1; // 14 TA for Mailbox 14
Uint16 TA15:1; // 15 TA for Mailbox 15
Uint16 TA16:1; // 16 TA for Mailbox 16
Uint16 TA17:1; // 17 TA for Mailbox 17
Uint16 TA18:1; // 18 TA for Mailbox 18
Uint16 TA19:1; // 19 TA for Mailbox 19
Uint16 TA20:1; // 20 TA for Mailbox 20
Uint16 TA21:1; // 21 TA for Mailbox 21
Uint16 TA22:1; // 22 TA for Mailbox 22
Uint16 TA23:1; // 23 TA for Mailbox 23
Uint16 TA24:1; // 24 TA for Mailbox 24
Uint16 TA25:1; // 25 TA for Mailbox 25
Uint16 TA26:1; // 26 TA for Mailbox 26
Uint16 TA27:1; // 27 TA for Mailbox 27
Uint16 TA28:1; // 28 TA for Mailbox 28
Uint16 TA29:1; // 29 TA for Mailbox 29
Uint16 TA30:1; // 30 TA for Mailbox 30
Uint16 TA31:1; // 31 TA for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTA_REG {
Uint32 all;
struct CANTA_BITS bit;
};
/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */
struct CANAA_BITS { // bit description
Uint16 AA0:1; // 0 AA for Mailbox 0
Uint16 AA1:1; // 1 AA for Mailbox 1
Uint16 AA2:1; // 2 AA for Mailbox 2
Uint16 AA3:1; // 3 AA for Mailbox 3
Uint16 AA4:1; // 4 AA for Mailbox 4
Uint16 AA5:1; // 5 AA for Mailbox 5
Uint16 AA6:1; // 6 AA for Mailbox 6
Uint16 AA7:1; // 7 AA for Mailbox 7
Uint16 AA8:1; // 8 AA for Mailbox 8
Uint16 AA9:1; // 9 AA for Mailbox 9
Uint16 AA10:1; // 10 AA for Mailbox 10
Uint16 AA11:1; // 11 AA for Mailbox 11
Uint16 AA12:1; // 12 AA for Mailbox 12
Uint16 AA13:1; // 13 AA for Mailbox 13
Uint16 AA14:1; // 14 AA for Mailbox 14
Uint16 AA15:1; // 15 AA for Mailbox 15
Uint16 AA16:1; // 16 AA for Mailbox 16
Uint16 AA17:1; // 17 AA for Mailbox 17
Uint16 AA18:1; // 18 AA for Mailbox 18
Uint16 AA19:1; // 19 AA for Mailbox 19
Uint16 AA20:1; // 20 AA for Mailbox 20
Uint16 AA21:1; // 21 AA for Mailbox 21
Uint16 AA22:1; // 22 AA for Mailbox 22
Uint16 AA23:1; // 23 AA for Mailbox 23
Uint16 AA24:1; // 24 AA for Mailbox 24
Uint16 AA25:1; // 25 AA for Mailbox 25
Uint16 AA26:1; // 26 AA for Mailbox 26
Uint16 AA27:1; // 27 AA for Mailbox 27
Uint16 AA28:1; // 28 AA for Mailbox 28
Uint16 AA29:1; // 29 AA for Mailbox 29
Uint16 AA30:1; // 30 AA for Mailbox 30
Uint16 AA31:1; // 31 AA for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANAA_REG {
Uint32 all;
struct CANAA_BITS bit;
};
/* eCAN Received Message Pending register (CANRMP) bit definitions */
struct CANRMP_BITS { // bit description
Uint16 RMP0:1; // 0 RMP for Mailbox 0
Uint16 RMP1:1; // 1 RMP for Mailbox 1
Uint16 RMP2:1; // 2 RMP for Mailbox 2
Uint16 RMP3:1; // 3 RMP for Mailbox 3
Uint16 RMP4:1; // 4 RMP for Mailbox 4
Uint16 RMP5:1; // 5 RMP for Mailbox 5
Uint16 RMP6:1; // 6 RMP for Mailbox 6
Uint16 RMP7:1; // 7 RMP for Mailbox 7
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