/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/*                                                                            */
/*                                                                            */
/******************************************************************************/
/*----------------------------------------------------------------------------*/
/* DESCRIPTION:  															  */
/*   																		  */
/* This is an example for EERPOM of C5509										  */
/*----------------------------------------------------------------------------*/
/* MODULE NAME... SPI EEPROM write and read 										  */
/* FILENAME...... boot.c    												  */
/* DATE CREATED.. Mon 03/5/2004	    										  */
/* COMPONENT..... 															  */
/* PREREQUISITS.. 															  */
/*----------------------------------------------------------------------------*/
/* DESCRIPTION:																  */  
/*   																		  */
/* this example is that write the SPI EEPROM  		  */
/*----------------------------------------------------------------------------*/

#include <csl.h>
#include <stdio.h>
#include <csl_pll.h>
#include <csl_mcbsp.h>
#include <csl_gpio.h>
#include <csl_irq.h>
#include <csl_chip.h>

#define SPI_WRITE 	  0x02000000
#define SPI_READ  	  0x03000000
#define SPI_WRITE_EN  0x06
#define SPI_WRITE_DI  0x04
#define SPI_WRITE_REG 0x0100
#define SPI_READ_REG  0x0500


/*鎖相環(huán)的設(shè)置*/
PLL_Config  myConfig      = {
  0,    //IAI: the PLL locks using the same process that was underway 
                //before the idle mode was entered
  1,    //IOB: If the PLL indicates a break in the phase lock, 
                //it switches to its bypass mode and restarts the PLL phase-locking 
                //sequence
  2,    //PLL multiply value; multiply 12 times
  0             //Divide by 2 PLL divide value; it can be either PLL divide value 
                //(when PLL is enabled), or Bypass-mode divide value
                //(PLL in bypass mode, if PLL multiply value is set to 1)
};


MCBSP_Handle hMcbsp;
Uint32 data_read[0x100] = {0};

Uint32 SPI_ReadSignal(Uint32 address);
void SPI_WrieSignal(Uint32 address,Uint32 data);

void main(void)
{
    Uint32 EEPROM_data = 0; 
    Uint32 i = 0;
    Uint32 EPROM_address = 0;
    /* Initialize CSL library - This is REQUIRED !!! */
    /*初始化CSL庫*/
    CSL_init();
    /*EMIF為全EMIF接口*/
    CHIP_RSET(XBSR,0x0a01);
	/*禁止所有中斷*/
	IRQ_globalDisable(); 
    /*確定方向?yàn)檩敵?/
    GPIO_RSET(IODIR,0xFF);
	/*設(shè)置系統(tǒng)的運(yùn)行速度為144MHz*/
    PLL_config(&myConfig);
  	
  	/*寫入數(shù)據(jù)*/
  	for(i = 0; i<0x100;)
  	{	
  		/*測試時(shí)，將數(shù)據(jù)寫完后，斷電后，重新上電打開CCS
  			將此行注釋掉，直接讀取數(shù)據(jù)，觀察是否正確*/
  		SPI_WrieSignal(EPROM_address,i);
  		/*讀回寫入的數(shù)據(jù)*/
		EEPROM_data = SPI_ReadSignal(EPROM_address);
		/*保存讀取的數(shù)據(jù)*/
		data_read[i] = EEPROM_data;
  		if(i != (data_read[i] & 0xFF))
  		{
 			for(;;){}
  		}
  		EPROM_address++;
  		i++;
  	} 
  	for(;;)
  	{}    	   	    	   
}

/*********************************************************************************/
/*		EEPROM write enable and write disable  									 */
/*********************************************************************************/
/*兩次操作之間的延時(shí)*/
void SPIEND_Delay()
{
	Uint32 j =0;
	for(j= 0;j<0x20;j++)
	{}
}
/*讀寫使能與禁止初始化，數(shù)據(jù)長度為8位*/
void SPI_writecominit(MCBSP_Handle hMcbsp)
{
   /****************************************************************/
   /* Place port in reset - setting XRST & RRST to 0               */
   /****************************************************************/
   /*進(jìn)行發(fā)送復(fù)位*/
   MCBSP_FSETH(hMcbsp, SPCR2, XRST,0);
   /*進(jìn)行接收復(fù)位*/
   MCBSP_FSETH(hMcbsp, SPCR1, RRST,0); 
   /*進(jìn)行分頻器復(fù)位*/
   MCBSP_FSETH(hMcbsp, SPCR2, GRST,0);
   /****************************************************************/
   /* Set values of all control registers                          */
   /****************************************************************/
   /*設(shè)置SPCR1寄存器,SPI時(shí)鐘停止模式*/
   MCBSP_FSETH(hMcbsp, SPCR1,CLKSTP,0x3);
   /*設(shè)置XCR1寄存器，單數(shù)據(jù)相，發(fā)送數(shù)據(jù)長度為8位*/
   MCBSP_FSETH(hMcbsp, XCR1, XFRLEN1,0x0);
   MCBSP_FSETH(hMcbsp, RCR1, RFRLEN1,0x0);
   MCBSP_FSETH(hMcbsp, XCR1, XWDLEN1,0x0);
   MCBSP_FSETH(hMcbsp, RCR1, RWDLEN1,0x0);
   /*設(shè)置XCR2寄存器，發(fā)送數(shù)據(jù)延時(shí)一個(gè)位*/
   MCBSP_FSETH(hMcbsp, XCR2, XDATDLY,0x1);
   MCBSP_FSETH(hMcbsp, RCR2, RDATDLY,0x1);
   /*設(shè)置PCR寄存器，設(shè)置BLCK為輸出，即MCBSP為Master；
   		            設(shè)置BFSX為輸出，并且其極性為低有效
   		            設(shè)置CLKXP為高*/
   MCBSP_FSETH(hMcbsp, PCR,CLKXP, 0x0);
   MCBSP_FSETH(hMcbsp, PCR,CLKRP, 0x1);
   MCBSP_FSETH(hMcbsp, PCR,CLKXM, 0x1);
   MCBSP_FSETH(hMcbsp, PCR,FSXM, 0x1);
   MCBSP_FSETH(hMcbsp, PCR,FSXP, 0x1);
   /*設(shè)置SRGR2，確定時(shí)鐘來源為內(nèi)部的CPU