?? dsp28_ecan.h
字號:
Uint16 RMP8:1; // 8 RMP for Mailbox 8
Uint16 RMP9:1; // 9 RMP for Mailbox 9
Uint16 RMP10:1; // 10 RMP for Mailbox 10
Uint16 RMP11:1; // 11 RMP for Mailbox 11
Uint16 RMP12:1; // 12 RMP for Mailbox 12
Uint16 RMP13:1; // 13 RMP for Mailbox 13
Uint16 RMP14:1; // 14 RMP for Mailbox 14
Uint16 RMP15:1; // 15 RMP for Mailbox 15
Uint16 RMP16:1; // 16 RMP for Mailbox 16
Uint16 RMP17:1; // 17 RMP for Mailbox 17
Uint16 RMP18:1; // 18 RMP for Mailbox 18
Uint16 RMP19:1; // 19 RMP for Mailbox 19
Uint16 RMP20:1; // 20 RMP for Mailbox 20
Uint16 RMP21:1; // 21 RMP for Mailbox 21
Uint16 RMP22:1; // 22 RMP for Mailbox 22
Uint16 RMP23:1; // 23 RMP for Mailbox 23
Uint16 RMP24:1; // 24 RMP for Mailbox 24
Uint16 RMP25:1; // 25 RMP for Mailbox 25
Uint16 RMP26:1; // 26 RMP for Mailbox 26
Uint16 RMP27:1; // 27 RMP for Mailbox 27
Uint16 RMP28:1; // 28 RMP for Mailbox 28
Uint16 RMP29:1; // 29 RMP for Mailbox 29
Uint16 RMP30:1; // 30 RMP for Mailbox 30
Uint16 RMP31:1; // 31 RMP for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRMP_REG {
Uint32 all;
struct CANRMP_BITS bit;
};
/* eCAN Received Message Lost register (CANRML) bit definitions */
struct CANRML_BITS { // bit description
Uint16 RML0:1; // 0 RML for Mailbox 0
Uint16 RML2:1; // 2 RML for Mailbox 2
Uint16 RML3:1; // 3 RML for Mailbox 3
Uint16 RML4:1; // 4 RML for Mailbox 4
Uint16 RML5:1; // 5 RML for Mailbox 5
Uint16 RML6:1; // 6 RML for Mailbox 6
Uint16 RML7:1; // 7 RML for Mailbox 7
Uint16 RML8:1; // 8 RML for Mailbox 8
Uint16 RML9:1; // 9 RML for Mailbox 9
Uint16 RML10:1; // 10 RML for Mailbox 10
Uint16 RML11:1; // 11 RML for Mailbox 11
Uint16 RML12:1; // 12 RML for Mailbox 12
Uint16 RML13:1; // 13 RML for Mailbox 13
Uint16 RML14:1; // 14 RML for Mailbox 14
Uint16 RML15:1; // 15 RML for Mailbox 15
Uint16 RML16:1; // 16 RML for Mailbox 16
Uint16 RML17:1; // 17 RML for Mailbox 17
Uint16 RML18:1; // 18 RML for Mailbox 18
Uint16 RML19:1; // 19 RML for Mailbox 19
Uint16 RML20:1; // 20 RML for Mailbox 20
Uint16 RML21:1; // 21 RML for Mailbox 21
Uint16 RML22:1; // 22 RML for Mailbox 22
Uint16 RML23:1; // 23 RML for Mailbox 23
Uint16 RML24:1; // 24 RML for Mailbox 24
Uint16 RML25:1; // 25 RML for Mailbox 25
Uint16 RML26:1; // 26 RML for Mailbox 26
Uint16 RML27:1; // 27 RML for Mailbox 27
Uint16 RML28:1; // 28 RML for Mailbox 28
Uint16 RML29:1; // 29 RML for Mailbox 29
Uint16 RML30:1; // 30 RML for Mailbox 30
Uint16 RML31:1; // 31 RML for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRML_REG {
Uint32 all;
struct CANRML_BITS bit;
};
/* eCAN Remote Frame Pending register (CANRFP) bit definitions */
struct CANRFP_BITS { // bit description
Uint16 RFP0:1; // 0 RFP for Mailbox 0
Uint16 RFP1:1; // 1 RFP for Mailbox 1
Uint16 RFP2:1; // 2 RFP for Mailbox 2
Uint16 RFP3:1; // 3 RFP for Mailbox 3
Uint16 RFP4:1; // 4 RFP for Mailbox 4
Uint16 RFP5:1; // 5 RFP for Mailbox 5
Uint16 RFP6:1; // 6 RFP for Mailbox 6
Uint16 RFP7:1; // 7 RFP for Mailbox 7
Uint16 RFP8:1; // 8 RFP for Mailbox 8
Uint16 RFP9:1; // 9 RFP for Mailbox 9
Uint16 RFP10:1; // 10 RFP for Mailbox 10
Uint16 RFP11:1; // 11 RFP for Mailbox 11
Uint16 RFP12:1; // 12 RFP for Mailbox 12
Uint16 RFP13:1; // 13 RFP for Mailbox 13
Uint16 RFP14:1; // 14 RFP for Mailbox 14
Uint16 RFP15:1; // 15 RFP for Mailbox 15
Uint16 RFP16:1; // 16 RFP for Mailbox 16
Uint16 RFP17:1; // 17 RFP for Mailbox 17
Uint16 RFP18:1; // 18 RFP for Mailbox 18
Uint16 RFP19:1; // 19 RFP for Mailbox 19
Uint16 RFP20:1; // 20 RFP for Mailbox 20
Uint16 RFP21:1; // 21 RFP for Mailbox 21
Uint16 RFP22:1; // 22 RFP for Mailbox 22
Uint16 RFP23:1; // 23 RFP for Mailbox 23
Uint16 RFP24:1; // 24 RFP for Mailbox 24
Uint16 RFP25:1; // 25 RFP for Mailbox 25
Uint16 RFP26:1; // 26 RFP for Mailbox 26
Uint16 RFP27:1; // 27 RFP for Mailbox 27
Uint16 RFP28:1; // 28 RFP for Mailbox 28
Uint16 RFP29:1; // 29 RFP for Mailbox 29
Uint16 RFP30:1; // 30 RFP for Mailbox 30
Uint16 RFP31:1; // 31 RFP for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANRFP_REG {
Uint32 all;
struct CANRFP_BITS bit;
};
/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */
struct CANGAM_BITS { // bits description
Uint16 GAM150:16; // 15:0
Uint16 GAM2816:13; // 28:16
Uint16 rsvd:2; // 30:29
Uint16 AMI:1; // 31 AMI bit
};
/* Allow access to the bit fields or entire register */
union CANGAM_REG {
Uint32 all;
struct CANGAM_BITS bit;
};
/* eCAN Master Control register (CANMC) bit definitions */
struct CANMC_BITS { // bits description
Uint16 MBNR:5; // 4:0 MBX # for CDR bit
Uint16 SRES:1; // 5 Soft reset
Uint16 STM:1; // 6 Self-test mode
Uint16 ABO:1; // 7 Auto bus-on
Uint16 CDR:1; // 8 Change data request
Uint16 WUBA:1; // 9 Wake-up on bus activity
Uint16 DBO:1; // 10 Data-byte order
Uint16 PDR:1; // 11 Power-down mode request
Uint16 CCR:1; // 12 Change configuration request
Uint16 SCM:1; // 13 SCC compatibility mode
Uint16 LNTM:1; // 14 LNT MSB clear bit
Uint16 LNTC:1; // 15 LNT clear bit thru mailbox 16
Uint16 SUSP:1; // 16 SUSPEND free/soft bit
Uint16 rsvd:15; // 31:17 reserved
};
/* Allow access to the bit fields or entire register */
union CANMC_REG {
Uint32 all;
struct CANMC_BITS bit;
};
/* eCAN Bit -timing configuration register (CANBTC) bit definitions */
struct CANBTC_BITS { // bits description
Uint16 TSEG2:3; // 2:0 TSEG2
Uint16 TSEG1:4; // 6:3 TSEG1
Uint16 SAM:1; // 7 Sample-point setting
Uint16 SJW:2; // 9:8 Synchroniztion Jump Width
Uint16 ERM:1; // 10 Edge resynchroniztion mode
Uint16 rsvd1:5; // 15:11 reserved
Uint16 BRP:8; // 23:16 Time quantum prescaler
Uint16 rsvd2:8; // 31:24 reserved
};
/* Allow access to the bit fields or entire register */
union CANBTC_REG {
Uint32 all;
struct CANBTC_BITS bit;
};
/* eCAN Error & Status register (CANES) bit definitions */
struct CANES_BITS { // bits description
Uint16 TM:1; // 0 TM
Uint16 RM:1; // 1 RM
Uint16 rsvd1:1; // 2 reserved
Uint16 PDA:1; // 3 Power-down acknowledge
Uint16 CCE:1; // 4 Change Configuration Enable
Uint16 SMA:1; // 5 Suspend Mode Acknowledge
Uint16 rsvd2:10; // 15:6 reserved
Uint16 EW:1; // 16 EW
Uint16 EP:1; // 17 EP
Uint16 BO:1; // 18 BO
Uint16 ACKE:1; // 19 ACKE
Uint16 SE:1; // 20 SE
Uint16 CRCE:1; // 21 CRCE
Uint16 SA1:1; // 22 SA1
Uint16 BE:1; // 23 BE
Uint16 FE:1; // 24 FE
Uint16 rsvd3:7; // 31:25 reserved
};
/* Allow access to the bit fields or entire register */
union CANES_REG {
Uint32 all;
struct CANES_BITS bit;
};
/* eCAN Transmit Error Counter register (CANTEC) bit definitions */
struct CANTEC_BITS { // bits description
Uint16 TEC:8; // 7:0 TEC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTEC_REG {
Uint32 all;
struct CANTEC_BITS bit;
};
/* eCAN Receive Error Counter register (CANREC) bit definitions */
struct CANREC_BITS { // bits description
Uint16 REC:8; // 7:0 REC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANREC_REG {
Uint32 all;
struct CANREC_BITS bit;
};
/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */
struct CANGIF0_BITS { // bits description
Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF0:1; // 8 WLIF0
Uint16 EPIF0:1; // 9 EPIF0
Uint16 BOIF0:1; // 10 BOIF0
Uint16 RMLIF0:1; // 11 RMLIF0
Uint16 WUIF0:1; // 12 WUIF0
Uint16 WDIF0:1; // 13 WDIF0
Uint16 AAIF0:1; // 14 AAIF0
Uint16 GMIF0:1; // 15 GMIF0
Uint16 TCOIF0:1; // 16 TCOIF0
Uint16 MAIF0:1; // 17 MAIF0
Uint16 rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF0_REG {
Uint32 all;
struct CANGIF0_BITS bit;
};
/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */
struct CANGIM_BITS { // bits description
Uint16 I0EN:1; // 0 Interrupt 0 enable
Uint16 I1EN:1; // 1 Interrupt 1 enable
Uint16 SIL:1; // 2 System Interrupt Level
Uint16 rsvd1:5; // 7:3 reserved
Uint16 WLIM:1; // 8 WLIM
Uint16 EPIM:1; // 9 EPIM
Uint16 BOIM:1; // 10 BOIM
Uint16 RMLIM:1; // 11 RMLIM
Uint16 WUIM:1; // 12 WUIM
Uint16 WDIM:1; // 13 WDIM
Uint16 AAIM:1; // 14 AAIM
Uint16 rsvd2:1; // 15 reserved
Uint16 TCOIM:1; // 16 TCOIM
Uint16 MAIM:1; // 17 MAIM
Uint16 rsvd3:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIM_REG {
Uint32 all;
struct CANGIM_BITS bit;
};
/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */
struct CANGIF1_BITS { // bits description
Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF1:1; // 8 WLIF1
Uint16 EPIF1:1; // 9 EPIF1
Uint16 BOIF1:1; // 11 BOIF1
Uint16 RMLIF1:1; // 11 RMLIF1
Uint16 WUIF1:1; // 12 WUIF1
Uint16 WDIF1:1; // 13 WDIF1
Uint16 AAIF1:1; // 14 AAIF1
Uint16 GMIF1:1; // 15 GMIF1
Uint16 TCOIF1:1; // 16 TCOIF1
Uint16 MAIF1:1; // 17 MAIF1
Uint16 rsvd2:14; // 31:18 reserved
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