%% Demo: Phase Locked Loop
% This demo shows the executable specifications and design with simulation
% capabilities of Simulink. It highlights:
%  
% 1. Creating conceptual models of signal processing systems and running
% simulations
%
% 2. Adding finite state machines to the design
%
% 3. Creating models of physical components (e.g. circuitery)
%
% 4. Using discrete-time signal to create mixed-signal models
%
% 5. Converting digital models to fixed-point
%
% 6. Optional: (not implemented yet) generating C and/or HDL

%% What is a Phase-Locked Loop?
% A phase-locked loop (PLL) is a closed-loop feedback control system that
% generates and outputs a signal in relation to the frequency and phase of
% an input ("reference") signal. A phase-locked loop circuit responds to
% both the frequency and the phase of the input signals, automatically
% raising or lowering the frequency of a controlled oscillator until it is
% matched to the reference in both frequency and phase.
% 
% This type of mechanism is widely used in radio, telecommunications,
% computers and other electronic applications where it is desired to
% stabilize a generated signal or to detect signals in the presence of
% noise. Since an integrated circuit can hold a complete phase-locked loop
% building block, the technique is widely used in modern electronic
% devices, with signal frequencies from a fraction of a cycle per second up
% to many gigahertz.  (Source: wikipedia.org.)


%% A linear Phase Locked Loop in Simulink
% The first step of the demo shows how to model and simulate a linear PLL
% that can track a 1 MHz reference signal.
%
% A classic or linear PLL uses a mixer as a phase detector. This yields a
% DC component that is proportional (but not linear) with the phase
% difference and a component at a frequency that is twice the input
% frequency. A loop filter is used to get rid of the second component. The
% output of the loop filter is fed into a VCO that increases the freqeuncy
% if there is a positive phase difference and that decreases the frequency
% if there is a negative phase difference.
%
% Start with the basic components of a PLL: a Multiply block (Math
% Library), an Analog Filter Design block (Filter Design library in the
% Signal Processing Blockset) and a Voltage Controlled Oscillator
% (Communications Blockset, Components sublibrary in the Synchronization
% library).
%
% Double click on the blocks to show how to set the parameters for each
% block:
%
% The Analog Filter Design block;
%    Design method: butterworth,
%    Filter type: Lowpass,
%    Filter order: 5,
%    Passband edge frequency: 1e6*2*pi.
%
% The VCO block;
%    Quiescent frequency: 1e6,
%    Input sensitivity: 1e5,
%    Initial phase: 0.

open_system('linearpll'); set_param(bdroot,'SimulationCommand', 'update')
sim(bdroot);

%%
% In order to simulate the system, we need a test input and vizualiation.
% To achieve this, add a Sine wave block (Simulink Sources Library) and a
% Scope block (Simulink Sinks library) to the model. Set the parameters of
% the Sine wave to:
%
% Sine Wave block;
%    Frequency: 2*pi*1e6,
%    All other parameters: default.
%
% Add another axes to the Scope block, and connect the two inputs to the
% outputs of the Sine Wave block and the VCO block. Change the simulation
% time to 50 periods (50e-6). Connect a second Scope block to the output of
% the Butterworth filter. Label the block appropriately. Run the
% simulation!

figure('Color', 'White');
plot(log_linearpll.time*1e6, [log_linearpll.signals.values]);
 grid; axis([0 10 -1 1]);legend('Reference', 'PLL');
xlabel('Time (\mus)'); set(gcf,'Position', [360   502   560   267]);
ylabel('Voltage (V)');

%%
% To assess the quality of the PLL we are going to look at the spectrum of
% the generated signal. Add a Spectrum Scope block from the Signal
% Processing Sinks library and change it's parameters:
%
% Spectrum Scope parameters;
%    Buffer input: on,
%    Buffer size: 512,
%    Buffer overlap: 256,
%    Window type: Kaiser,
%    Beta: 5,
%    Specify FFT length: off,
%    Number of Spectral averages: 1.

pwelch(log_linearpll.signals(2).values,kaiser(1024,5),512,[],1e8)

%%
% To test how robust the PLL behaves to phase and frequency differences we
% can change the Frequency and Phase offset parameters of the Sine. For
% example, the PLL locks at frequencies up to about 1.05 MHz, but it fails
% to lock at 1.1 MHz. Also, for frequencies other then 1 MHz, the generated
% signal will have a phase offset with respect to the carrier (the reason
% being that the butterworth filter doesn't have a pole at zero (no pure
% integrator). Also note the ripple on the control signal, which is due to
% the second harmonics of the multiplication.

%% A charge-pump PLL with digital Phase-Frequency Detector in Simulink
% Better results can be achieved with a charge pump and a loop filter. The
% charge pump, "pumps" current into a 2nd order loop filter. The branch
% voltage of the loop filter is used as input to the VCO. A digital phase
% frequency detector (PFD) determines whether a positive or negative
% current is pumped into the filter. Phase lead corresponds to a negative
% frequency (output and thus VCO frequency decreases) whereas phase lag
% corresponds to a positive current.
% 
% The PFD is typically a finite state machine that reponds to
% zero-crossings of the input signals. If the reference signal has a
% positive edge first a switch is turned on that pumps a positive
% current into the loop filter, until a positive edge of the VCO signal is
% detected (phase lag).

%%
% We'll start by creating a behavioral model of the PLL. To model the PFD
% we use a Stateflow machine. Create the chart according to the diagram
% below:
%%
% <<pfd.jpg>>
%
%%
% Update the diagram and create input events (Rising Edge) for Ref and Var
% and an output variable for s. To be able to feed the reference signal and
% VCO signal to the Chart, use a Mux block (Simulink routing library)
%
% Implement the charge pump with a Gain block. Set the gain parameter to
% 260e-6 (Ampere). A behavioral model for the loop filter can be created
% with a simple Transfer Fcn block. To set the parameters of this block, we
% need to find the transfer function for the loop filter. Applying the
% Laplace transform to the differential equations yields:
%
%%
% $$ G(s) = \frac{sR_1C_1 + 1}{s^2C_1C_2R_1 + s(C_1 + C_2)} $$
%
% Set the Numerator coefficient of the Transfer Fcn block to [R1*C1, 1], and
% set the Denominator coefficient to [C1*C2*R1, (C1+C2), 0]. Next, adjust
% the loop gain by changing the Input Sensitivity of the VCO to 3e5. Change
% the Initial phase to -pi/2.
%
% Assign values to variables |C1|, |C2| and |R1| in the MATLAB workspace:
%
%  C2 = 17e-12;
%  C1 = 82e-12;
%  R1 = 23e3;
%
% Run the simulation with the Stateflow Chart open to see the animation.
%
% Experiment with the Phase offset and Frequency of the Sine Wave block to
% test the PLL.

open_system('cppll'); set_param(bdroot,'SimulationCommand', 'update')

%% An implementation for the PFD, Charge Pump and Loop filter
% In the previous model we used behaviorable models for the PFD (state
% chart), charge pump (Gain) and loop filter (transfer function). Simulink
% also has the capabilities to simulate an physical implementation for
% these three components.

%%
% Open the model |powerpll| to see an example.

open_system('powerpll'); set_param(bdroot,'SimulationCommand', 'update')

%%
% In this example the phase frequency detector is implemented by two
% flipflops and a NAND gate. The charge pump and loop filter are
% implemented using blocks from the SimPowerSystem blockset. This extension
% to Simulink makes it possible to draw electrical circuits directly in
% Simulink. This eliminates the neccesity to derive differential equations
% and transfer functions and facilitates experimenting with different
% network topologies.
%