?? 2410addr.s
字號:
PWR_REG EQU 0x52000144 ;Power management
EP_INT_REG EQU 0x52000148 ;EP Interrupt pending and clear
USB_INT_REG EQU 0x52000158 ;USB Interrupt pending and clear
EP_INT_EN_REG EQU 0x5200015c ;Interrupt enable
USB_INT_EN_REG EQU 0x5200016c
FRAME_NUM1_REG EQU 0x52000170 ;Frame number lower byte
FRAME_NUM2_REG EQU 0x52000174 ;Frame number lower byte
INDEX_REG EQU 0x52000178 ;Register index
MAXP_REG EQU 0x52000180 ;Endpoint max packet
EP0_CSR EQU 0x52000184 ;Endpoint 0 status
IN_CSR1_REG EQU 0x52000184 ;In endpoint control status
IN_CSR2_REG EQU 0x52000188
OUT_CSR1_REG EQU 0x52000190 ;Out endpoint control status
OUT_CSR2_REG EQU 0x52000194
OUT_FIFO_CNT1_REG EQU 0x52000198 ;Endpoint out write count
OUT_FIFO_CNT2_REG EQU 0x5200019c
EP0_FIFO EQU 0x520001c0 ;Endpoint 0 FIFO
EP1_FIFO EQU 0x520001c4 ;Endpoint 1 FIFO
EP2_FIFO EQU 0x520001c8 ;Endpoint 2 FIFO
EP3_FIFO EQU 0x520001cc ;Endpoint 3 FIFO
EP4_FIFO EQU 0x520001d0 ;Endpoint 4 FIFO
EP1_DMA_CON EQU 0x52000200 ;EP1 DMA interface control
EP1_DMA_UNIT EQU 0x52000204 ;EP1 DMA Tx unit counter
EP1_DMA_FIFO EQU 0x52000208 ;EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L EQU 0x5200020c ;EP1 DMA total Tx counter
EP1_DMA_TTC_M EQU 0x52000210
EP1_DMA_TTC_H EQU 0x52000214
EP2_DMA_CON EQU 0x52000218 ;EP2 DMA interface control
EP2_DMA_UNIT EQU 0x5200021c ;EP2 DMA Tx unit counter
EP2_DMA_FIFO EQU 0x52000220 ;EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L EQU 0x52000224 ;EP2 DMA total Tx counter
EP2_DMA_TTC_M EQU 0x52000228
EP2_DMA_TTC_H EQU 0x5200022c
EP3_DMA_CON EQU 0x52000240 ;EP3 DMA interface control
EP3_DMA_UNIT EQU 0x52000244 ;EP3 DMA Tx unit counter
EP3_DMA_FIFO EQU 0x52000248 ;EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L EQU 0x5200024c ;EP3 DMA total Tx counter
EP3_DMA_TTC_M EQU 0x52000250
EP3_DMA_TTC_H EQU 0x52000254
EP4_DMA_CON EQU 0x52000258 ;EP4 DMA interface control
EP4_DMA_UNIT EQU 0x5200025c ;EP4 DMA Tx unit counter
EP4_DMA_FIFO EQU 0x52000260 ;EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L EQU 0x52000264 ;EP4 DMA total Tx counter
EP4_DMA_TTC_M EQU 0x52000268
EP4_DMA_TTC_H EQU 0x5200026c
]
;=================
; WATCH DOG TIMER
;=================
WTCON EQU 0x53000000 ;Watch-dog timer mode
WTDAT EQU 0x53000004 ;Watch-dog timer data
WTCNT EQU 0x53000008 ;Eatch-dog timer count
;=================
; IIC
;=================
IICCON EQU 0x54000000 ;IIC control
IICSTAT EQU 0x54000004 ;IIC status
IICADD EQU 0x54000008 ;IIC address
IICDS EQU 0x5400000c ;IIC data shift
;=================
; IIS
;=================
IISCON EQU 0x55000000 ;IIS Control
IISMOD EQU 0x55000004 ;IIS Mode
IISPSR EQU 0x55000008 ;IIS Prescaler
IISFCON EQU 0x5500000c ;IIS FIFO control
[ BIG_ENDIAN__
IISFIFO EQU 0x55000012 ;IIS FIFO entry
| ;Little Endian
IISFIFO EQU 0x55000010 ;IIS FIFO entry
]
;=================
; I/O PORT
;=================
GPACON EQU 0x56000000 ;Port A control
GPADAT EQU 0x56000004 ;Port A data
GPBCON EQU 0x56000010 ;Port B control
GPBDAT EQU 0x56000014 ;Port B data
GPBUP EQU 0x56000018 ;Pull-up control B
GPCCON EQU 0x56000020 ;Port C control
GPCDAT EQU 0x56000024 ;Port C data
GPCUP EQU 0x56000028 ;Pull-up control C
GPDCON EQU 0x56000030 ;Port D control
GPDDAT EQU 0x56000034 ;Port D data
GPDUP EQU 0x56000038 ;Pull-up control D
GPECON EQU 0x56000040 ;Port E control
GPEDAT EQU 0x56000044 ;Port E data
GPEUP EQU 0x56000048 ;Pull-up control E
GPFCON EQU 0x56000050 ;Port F control
GPFDAT EQU 0x56000054 ;Port F data
GPFUP EQU 0x56000058 ;Pull-up control F
GPGCON EQU 0x56000060 ;Port G control
GPGDAT EQU 0x56000064 ;Port G data
GPGUP EQU 0x56000068 ;Pull-up control G
GPHCON EQU 0x56000070 ;Port H control
GPHDAT EQU 0x56000074 ;Port H data
GPHUP EQU 0x56000078 ;Pull-up control H
MISCCR EQU 0x56000080 ;Miscellaneous control
DCKCON EQU 0x56000084 ;DCLK0/1 control
EXTINT0 EQU 0x56000088 ;External interrupt control register 0
EXTINT1 EQU 0x5600008c ;External interrupt control register 1
EXTINT2 EQU 0x56000090 ;External interrupt control register 2
EINTFLT0 EQU 0x56000094 ;Reserved
EINTFLT1 EQU 0x56000098 ;Reserved
EINTFLT2 EQU 0x5600009c ;External interrupt filter control register 2
EINTFLT3 EQU 0x560000a0 ;External interrupt filter control register 3
EINTMASK EQU 0x560000a4 ;External interrupt mask
EINTPEND EQU 0x560000a8 ;External interrupt pending
GSTATUS0 EQU 0x560000ac ;External pin status
GSTATUS1 EQU 0x560000b0 ;Chip ID(0x32410000)
GSTATUS2 EQU 0x560000b4 ;Reset type
GSTATUS3 EQU 0x560000b8 ;Saved data0(32-bit) before entering POWER_OFF mode
GSTATUS4 EQU 0x560000bc ;Saved data1(32-bit) before entering POWER_OFF mode
;=================
; RTC
;=================
[ BIG_ENDIAN__
RTCCON EQU 0x57000043 ;RTC control
TICNT EQU 0x57000047 ;Tick time count
RTCALM EQU 0x57000053 ;RTC alarm control
ALMSEC EQU 0x57000057 ;Alarm second
ALMMIN EQU 0x5700005b ;Alarm minute
ALMHOUR EQU 0x5700005f ;Alarm Hour
ALMDATE EQU 0x57000063 ;Alarm day <-- May 06, 2002 SOP
ALMMON EQU 0x57000067 ;Alarm month
ALMYEAR EQU 0x5700006b ;Alarm year
RTCRST EQU 0x5700006f ;RTC round reset
BCDSEC EQU 0x57000073 ;BCD second
BCDMIN EQU 0x57000077 ;BCD minute
BCDHOUR EQU 0x5700007b ;BCD hour
BCDDATE EQU 0x5700007f ;BCD day <-- May 06, 2002 SOP
BCDDAY EQU 0x57000083 ;BCD date <-- May 06, 2002 SOP
BCDMON EQU 0x57000087 ;BCD month
BCDYEAR EQU 0x5700008b ;BCD year
| ;Little Endian
RTCCON EQU 0x57000040 ;RTC control
TICNT EQU 0x57000044 ;Tick time count
RTCALM EQU 0x57000050 ;RTC alarm control
ALMSEC EQU 0x57000054 ;Alarm second
ALMMIN EQU 0x57000058 ;Alarm minute
ALMHOUR EQU 0x5700005c ;Alarm Hour
ALMDATE EQU 0x57000060 ;Alarm day <-- May 06, 2002 SOP
ALMMON EQU 0x57000064 ;Alarm month
ALMYEAR EQU 0x57000068 ;Alarm year
RTCRST EQU 0x5700006c ;RTC round reset
BCDSEC EQU 0x57000070 ;BCD second
BCDMIN EQU 0x57000074 ;BCD minute
BCDHOUR EQU 0x57000078 ;BCD hour
BCDDATE EQU 0x5700007c ;BCD day <-- May 06, 2002 SOP
BCDDAY EQU 0x57000080 ;BCD date <-- May 06, 2002 SOP
BCDMON EQU 0x57000084 ;BCD month
BCDYEAR EQU 0x57000088 ;BCD year
] ;RTC
;=================
; ADC
;=================
ADCCON EQU 0x58000000 ;ADC control
ADCTSC EQU 0x58000004 ;ADC touch screen control
ADCDLY EQU 0x58000008 ;ADC start or Interval Delay
ADCDAT0 EQU 0x5800000c ;ADC conversion data 0
ADCDAT1 EQU 0x58000010 ;ADC conversion data 1
;=================
; SPI
;=================
SPCON0 EQU 0x59000000 ;SPI0 control
SPSTA0 EQU 0x59000004 ;SPI0 status
SPPIN0 EQU 0x59000008 ;SPI0 pin control
SPPRE0 EQU 0x5900000c ;SPI0 baud rate prescaler
SPTDAT0 EQU 0x59000010 ;SPI0 Tx data
SPRDAT0 EQU 0x59000014 ;SPI0 Rx data
SPCON1 EQU 0x59000020 ;SPI1 control
SPSTA1 EQU 0x59000024 ;SPI1 status
SPPIN1 EQU 0x59000028 ;SPI1 pin control
SPPRE1 EQU 0x5900002c ;SPI1 baud rate prescaler
SPTDAT1 EQU 0x59000030 ;SPI1 Tx data
SPRDAT1 EQU 0x59000034 ;SPI1 Rx data
;=================
; SD Interface
;=================
SDICON EQU 0x5a000000 ;SDI control
SDIPRE EQU 0x5a000000 ;SDI baud rate prescaler
SDICmdArg EQU 0x5a000000 ;SDI command argument
SDICmdCon EQU 0x5a000000 ;SDI command control
SDICmdSta EQU 0x5a000000 ;SDI command status
SDIRSP0 EQU 0x5a000000 ;SDI response 0
SDIRSP1 EQU 0x5a000000 ;SDI response 1
SDIRSP2 EQU 0x5a000000 ;SDI response 2
SDIRSP3 EQU 0x5a000000 ;SDI response 3
SDIDTimer EQU 0x5a000000 ;SDI data/busy timer
SDIBSize EQU 0x5a000000 ;SDI block size
SDIDatCon EQU 0x5a000000 ;SDI data control
SDIDatCnt EQU 0x5a000000 ;SDI data remain counter
SDIDatSta EQU 0x5a000000 ;SDI data status
SDIFSTA EQU 0x5a000000 ;SDI FIFO status
SDIIntMsk EQU 0x5a000000 ;SDI interrupt mask
SDIDAT EQU 0x5a00003c ;SDI data
;=================
; PENDING BIT
;=================
BIT_EINT0 EQU (0x1)
BIT_EINT1 EQU (0x1<<1)
BIT_EINT2 EQU (0x1<<2)
BIT_EINT3 EQU (0x1<<3)
BIT_EINT4_7 EQU (0x1<<4)
BIT_EINT8_23 EQU (0x1<<5)
BIT_NOTUSED6 EQU (0x1<<6)
BIT_BAT_FLT EQU (0x1<<7)
BIT_TICK EQU (0x1<<8)
BIT_WDT EQU (0x1<<9)
BIT_TIMER0 EQU (0x1<<10)
BIT_TIMER1 EQU (0x1<<11)
BIT_TIMER2 EQU (0x1<<12)
BIT_TIMER3 EQU (0x1<<13)
BIT_TIMER4 EQU (0x1<<14)
BIT_UART2 EQU (0x1<<15)
BIT_LCD EQU (0x1<<16)
BIT_DMA0 EQU (0x1<<17)
BIT_DMA1 EQU (0x1<<18)
BIT_DMA2 EQU (0x1<<19)
BIT_DMA3 EQU (0x1<<20)
BIT_SDI EQU (0x1<<21)
BIT_SPI0 EQU (0x1<<22)
BIT_UART1 EQU (0x1<<23)
BIT_NOTUSED24 EQU (0x1<<24)
BIT_USBD EQU (0x1<<25)
BIT_USBH EQU (0x1<<26)
BIT_IIC EQU (0x1<<27)
BIT_UART0 EQU (0x1<<28)
BIT_SPI1 EQU (0x1<<29)
BIT_RTC EQU (0x1<<30)
BIT_ADC EQU (0x1<<31)
BIT_ALLMSK EQU (0xffffffff)
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