library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;              

entity pass is
 port(
    start:in std_logic;
    freq_in: in std_logic_vector(7 downto 0);   
    freq_out:out std_logic_vector(7 downto 0));
end pass;

architecture behave of pass is
begin 
process(start)
begin
if(start'event and start='1')then
  freq_out<=freq_in;
end if;
end process;
end behave;