// Force all valid interrupts for Group 4
       PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4; 

	   // Enable Global interrupts
	   EINT;

	   // Wait for all group 4 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR4.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");	
	   
// CASE 5:
//     Force all group 5 interrupts at once by writing to the PIEIFR5 register

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   
              
       // Enable PIE group 5 interrupts 1-8 
       PieCtrlRegs.PIEIER5.all = 0x00FF;

	   // Make sure PIEACK for group 5 is clear (default after reset)
       PieCtrlRegs.PIEACK.all = M_INT5;

       // Enable CPU INT5
       IER |= (M_INT5);

       // Force all valid interrupts for Group 5
       PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;  

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 5 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR5.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");
	   
// CASE 6:
//     Force all group 6 interrupts at once by writing to the PIEIFR6 register

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   
              
       // Enable PIE group 6 interrupts 1-8 
       PieCtrlRegs.PIEIER6.all = 0x00FF;

	   // Make sure PIEACK for group 6 is clear (default after reset)
       PieCtrlRegs.PIEACK.all = M_INT6;	   
              
       // Enable CPU INT6
       IER |= (M_INT6);

       // Force all valid interrupts for Group 6
       PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;  

	   // Enable Global interrupts
	   EINT;
	   
	   
	   // Wait for all group 6 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR6.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");

// CASE 8:
//     Force all group 9 interrupts at once by writing to the PIEIFR4 register

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;    

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   
       
       // Enable PIE group 9 interrupts 1-8 
       PieCtrlRegs.PIEIER9.all = 0x00FF;
       
	   // Make sure PIEACK for group 9 is clear (default after reset)
       PieCtrlRegs.PIEACK.all = M_INT9;

       // Enable CPU INT9
       IER |= (M_INT9);

       // Force all valid interrupts for Group 9
       PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;  

	   // Enable Global interrupts
	   EINT;

	   // Wait for all group 9 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR9.all != 0x0000 ){}
	   
       // Stop here and check the order the ISR's were serviced in the
       // ISRTrace
	   asm("        ESTOP0");	
	   	
// CASE 9:
//     Force all group 1 and group 2 interrupts at once

       // Setup next test - fire interrupts from Group 1 and Group 2

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   

       // Enable PIE group 1 and group 2 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;

	   // Make sure PIEACK for group 1 & 2 are clear (default after reset)
       PieCtrlRegs.PIEACK.all = (M_INT3 | M_INT2);

       // Enable CPU INT1 and INT2
       IER |= (M_INT1|M_INT2);
              
       // Force all valid interrupts for Group 1 and from Group 2
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 1 and group 2 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
	   
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	   


// CASE 10:
//     Force all group 1 and group 2 and group 3 interrupts at once

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   
       
       // Enable PIE group 1, 2 and 3 interrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;

	   // Make sure PIEACK for group 1, 2 & 3 are clear (default after reset)
       PieCtrlRegs.PIEACK.all = (M_INT3|M_INT2|M_INT3);

       // Enable CPU INT1, INT2 & INT3
       IER |= (M_INT1|M_INT2|M_INT3);
       
       // Force all valid interrupts for Group1, 2 and 3
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  
       PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;  

	   // Enable Global interrupts
	   EINT;
	   
	   // Wait for all group 1 and group 2 and group 3 interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 
	      || PieCtrlRegs.PIEIFR3.all != 0x0000 ) {}
	      
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	


// CASE 11:
//     Force all used PIE interrupts at once

       // Prepare for the test:
	   // Disable interrupts 
	   // Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
	   DINT;
	   for(i = 0; i < 50; i++) ISRTrace[i] = 0;
	   ISRTraceIndex = 0;
       InitPieCtrl();
       IER = 0;
       IFR &= 0;

       // Enable the PIE block
       PieCtrlRegs.PIECRTL.bit.ENPIE = 1;   

       // Enable all PIE group iterrupts 1-8 
       PieCtrlRegs.PIEIER1.all = 0x00FF;
       PieCtrlRegs.PIEIER2.all = 0x00FF;
       PieCtrlRegs.PIEIER3.all = 0x00FF;
       PieCtrlRegs.PIEIER4.all = 0x00FF;
       PieCtrlRegs.PIEIER5.all = 0x00FF;
       PieCtrlRegs.PIEIER6.all = 0x00FF;
       PieCtrlRegs.PIEIER9.all = 0x00FF;

	   // Make sure PIEACK for group 1, 2, 3, 4, 5, 6 and 9 are clear (default after reset)
       PieCtrlRegs.PIEACK.all = (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);

       // Enable CPU INT1, INT2, INT3, INT4, INT5, INT6 and INT9
       IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);
              
       // Force all valid interrupts for all PIE groups
       PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;  
       PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;  
       PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;  
       PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;  
       PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;  
       PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;  
       PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;  

	   // Enable Global interrupts - CPU level
	   EINT;
	   
	   // Wait for all group interrupts to be serviced
	   while(PieCtrlRegs.PIEIFR1.all != 0x0000 
	      || PieCtrlRegs.PIEIFR2.all != 0x0000 
	      || PieCtrlRegs.PIEIFR3.all != 0x0000 
          || PieCtrlRegs.PIEIFR4.all != 0x0000 
	      || PieCtrlRegs.PIEIFR5.all != 0x0000 
	      || PieCtrlRegs.PIEIFR6.all != 0x0000 
	      || PieCtrlRegs.PIEIFR9.all != 0x0000 ) {}
	      
	   // Check the ISRTrace to determine which order the ISR Routines completed
	   asm("        ESTOP0");	

} 	

//===========================================================================
// No more.
//===========================================================================