LIBRARY ieee;                        --除法器程序
USE ieee.std_logic_1164.all;

ENTITY div16div8 IS
PORT	(
	  a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
      b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	  sh: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      yushu:OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END  div16div8;
ARCHITECTURE SYN OF div16div8 IS

COMPONENT lpm_divide
PORT (numer: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
      denom: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	  quotient: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);	
      remain: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 
);
end component  lpm_divide; 

attribute  black_box:boolean;
attribute   LPM_WIDTHn: POSITIVE;
attribute   LPM_WIDTHd: POSITIVE;
attribute   black_box of lpm_divide: component is true;
attribute   LPM_WIDTHn of lpm_divide: component is 16;
attribute   LPM_WIDTHd of lpm_divide: component is 8;

BEGIN
I1: lpm_divide port map(
	      a,
	      b, 		   
		  sh,
	    yushu);
end architecture syn;