// This is generated from an EXCEL sheel - DO NOT EDIT// Generated on 8/17/2005 10:13:35 AM for BONO_P3_02_00// ############################################################################// #                                                                          #// #                    BONO specific bono_memory_map.equ                     #// #                    Freescale Confidential Proprietary                    #// # Purpose:                                                                 #// #   This file is used by the compilers/assembler to decode the memory map  #// #                                                                          #// # Description                                                              #// #   This file list out each individual memory location for decoding        #// #                                                                          #// # Initial version writen By                                                #// #   Kevin Shi (kevin.shi@freescale.com)                                    #// #                                                                          #// # Date                                                                     #// #   28 Apr 2005                                                            #// #                                                                          #// # Revisions                                                                #// #    Date       By           Description of changes                        #// #  10 Jan 2005  Kevin Shi    Initial release for Bono.                     #// #  28 Apr 2005  Kevin Shi    Updated release for Bono 1.0 RTL.             #// #  12 May 2005  Kevin Shi    Updated VRAM base address for Bono 1.0 RTL.   #// #  12 May 2005  Kevin Shi    Updated SYS register address for Bono 1.0 RTL #// #  30 May 2005  Kevin Shi    Updated WDOG register, PORTHOLE address.      #// #  10 Jun 2005  Kevin Shi    Added PCMCF address.                          #// #  15 Jun 2005  Kevin Shi    Updated SSI register.                         #// #  20 Jun 2005  Kevin Shi    Updated IIM, USB. Remove RNGA.                #// #  29 Jun 2005  Kevin Shi    Updated SDHC registers.                       #// #  17 Aug 2005  Kevin Shi    Added more user events                        #// #                                                                          #// ############################################################################// Memory Map// ----------// $0000_0000 - $0000_3FFF BROM// $0000_4000 - $0040_3FFF reserved// $0040_4000 - $007F_FFFF BROM// $0080_0000 - $0FFF_FFFF reserved// $1000_0000 - $1000_0FFF AIPI1// $1000_1000 - $1000_1FFF DMA// $1000_2000 - $1000_2FFF WDOG// $1000_3000 - $1000_3FFF GPT1// $1000_4000 - $1000_4FFF GPT2// $1000_5000 - $1000_5FFF GPT3// $1000_6000 - $1000_6FFF PWM// $1000_7000 - $1000_7FFF RTC// $1000_8000 - $1000_8FFF KPP// $1000_9000 - $1000_9FFF OWIRE// $1000_A000 - $1000_AFFF UART1// $1000_B000 - $1000_BFFF UART2// $1000_C000 - $1000_CFFF UART3// $1000_D000 - $1000_DFFF UART4// $1000_E000 - $1000_EFFF CSPI1// $1000_F000 - $1000_FFFF CSPI2// $1001_0000 - $1001_0FFF SSI1// $1001_1000 - $1001_1FFF SSI2// $1001_2000 - $1001_2FFF I2C1// $1001_3000 - $1001_3FFF SDHC1// $1001_4000 - $1001_4FFF SDHC2// $1001_5000 - $1001_5FFF GPIO// $1001_6000 - $1001_6FFF AUDMUX// $1001_7000 - $1001_7FFF CSPI3// $1001_8000 - $1001_8FFF MSHC// $1001_9000 - $1001_9FFF GPT4// $1001_A000 - $1001_AFFF GPT5// $1001_B000 - $1001_BFFF UART5// $1001_C000 - $1001_CFFF UART6// $1001_D000 - $1001_DFFF I2C2// $1001_E000 - $1001_EFFF SDHC3// $1001_F000 - $1001_FFFF GPT6// $1002_0000 - $1002_0FFF AIPI2// $1002_1000 - $1002_1FFF LCDC// $1002_2000 - $1002_2FFF SLCDC// $1002_3000 - $1002_3FFF H264// $1002_4000 - $1002_4FFF USB// $1002_5000 - $1002_5FFF SAHARA// $1002_6000 - $1002_6FFF EMMA// $1002_7000 - $1002_7FFF CRM and SYS// $1002_8000 - $1002_8FFF IIM// $1002_9000 - $1002_9FFF reserved// $1002_A000 - $1002_AFFF RTIC// $1002_B000 - $1002_BFFF FEC// $1002_C000 - $1002_CFFF SCC// $1002_D000 - $1002_DFFF SCC// $1002_E000 - $1002_EFFF reserved// $1003_0000 - $1003_0FFF reserved// $1003_1000 - $1003_1FFF reserved// $1003_2000 - $1003_2FFF reserved// $1003_3000 - $1003_3FFF reserved// $1003_4000 - $1003_4FFF reserved// $1003_5000 - $1003_5FFF reserved// $1003_6000 - $1003_6FFF reserved// $1003_7000 - $1003_7FFF reserved// $1003_8000 - $1003_8FFF reserved// $1003_9000 - $1003_9FFF reserved// $1003_A000 - $1003_AFFF reserved// $1003_B000 - $1003_BFFF ETB RAM// $1003_C000 - $1003_CFFF EBT RAM// $1003_D000 - $1003_DFFF ETB REGS// $1003_E000 - $1003_EFFF JAM// $1003_F000 - $1003_FFFF MAX// $1004_0000 - $1004_0FFF AITC// $1004_1000 - $1004_1FFF ROMPATCH// $1004_2000 - $1004_2FFF reserved// $1004_3000 - $1004_3FFF reserved// $1004_4000 - $7FFF_FFFF reserved// $8000_0000 - $8000_0FFF CSI// $8000_1000 - $8000_1FFF ATA// $8000_2000 - $9FFF_FFFF reserved// $A000_0000 - $AFFF_FFFF External Memory (CSD0)// $B000_0000 - $BFFF_FFFF External Memory (CSD1)// $C000_0000 - $C7FF_FFFF External Memory (CS0)// $C800_0000 - $CFFF_FFFF External Memory (CS1)// $D000_0000 - $D1FF_FFFF External Memory (CS2)// $D200_0000 - $D3FF_FFFF External Memory (CS3)// $D400_0000 - $D5FF_FFFF External Memory (CS4)// $D600_0000 - $D7FF_FFFF External Memory (CS5)// $D800_0000 - $D800_0FFF External Memory (NFC)// $D800_1000 - $D800_1FFF External Memory (ESDCTL)// $D800_2000 - $D800_2FFF External Memory (WEIM)// $D800_3000 - $D800_3FFF External Memory (M3IF)// $D800_4000 - $D800_4FFF External Memory (PCMCIA)// $D800_5000 - $DBFF_FFFF External Memory reserved// $DC00_0000 - $DFFF_FFFF External Memory (PCMCIA/CF)// $E000_0000 - $FFEF_FFFF reserved// $FFFF_4C00 - $FFFF_FFFF VRAM// #########################################// # BOOT ROM                              #// # $0000_0000 to $0000_3FFF              #// # $0040_4000 to $007F_FFFF              #// ##########################################define BOOTROM1_ADDR_BOT        0x00000000#define BOOTROM1_PHY_SIZE        0x00004000#define BOOTROM1_ASS_SIZE        0x00004000#define BOOTROM2_ADDR_BOT        0x00404000#define BOOTROM2_PHY_SIZE        0x003F4000#define BOOTROM2_ASS_SIZE        0x003F4000// #########################################// # AIPI1                                 #// # $1000_0000 to $1000_0FFF              #// ##########################################define AIPI1_BASE_ADDR          0x10000000#define AIPI1_PSR0               (AIPI1_BASE_ADDR+0x00)     // 32bit Peripheral Size Reg 0#define AIPI1_PSR1               (AIPI1_BASE_ADDR+0x04)     // 32bit Peripheral Size Reg 1#define AIPI1_PAR                (AIPI1_BASE_ADDR+0x08)     // 32bit Peripheral Access Reg// #########################################// # DMA                                   #// # $1000_1000 to $1000_1FFF              #// ##########################################define DMA_BASE_ADDR            0x10001000#define DMA_SYS_BASE             (DMA_BASE_ADDR+0x000)      // base location for system#define DMA_M2D_BASE             (DMA_BASE_ADDR+0x040)      // base location for 2D memory reg#define DMA_CH0_BASE             (DMA_BASE_ADDR+0x080)      // base location for channel 0#define DMA_CH1_BASE             (DMA_BASE_ADDR+0x0C0)      // base location for channel 1#define DMA_CH2_BASE             (DMA_BASE_ADDR+0x100)      // base location for channel 2#define DMA_CH3_BASE             (DMA_BASE_ADDR+0x140)      // base location for channel 3#define DMA_CH4_BASE             (DMA_BASE_ADDR+0x180)      // base location for channel 4#define DMA_CH5_BASE             (DMA_BASE_ADDR+0x1C0)      // base location for channel 5#define DMA_CH6_BASE             (DMA_BASE_ADDR+0x200)      // base location for channel 6#define DMA_CH7_BASE             (DMA_BASE_ADDR+0x240)      // base location for channel 7#define DMA_CH8_BASE             (DMA_BASE_ADDR+0x280)      // base location for channel 8#define DMA_CH9_BASE             (DMA_BASE_ADDR+0x2C0)      // base location for channel 9#define DMA_CH10_BASE            (DMA_BASE_ADDR+0x300)      // base location for channel 10#define DMA_CH11_BASE            (DMA_BASE_ADDR+0x340)      // base location for channel 11#define DMA_CH12_BASE            (DMA_BASE_ADDR+0x380)      // base location for channel 12#define DMA_CH13_BASE            (DMA_BASE_ADDR+0x3C0)      // base location for channel 13#define DMA_CH14_BASE            (DMA_BASE_ADDR+0x400)      // base location for channel 14#define DMA_CH15_BASE            (DMA_BASE_ADDR+0x440)      // base location for channel 15#define DMA_TEST_BASE            (DMA_BASE_ADDR+0x480)      // base location for test registers#define DMA_DCR                  (DMA_SYS_BASE+0x000)       // 32bit dma control reg