?? comscope.vhd
字號:
SELECTED_STATE_2 <= STATE_2_BIT_SIGNAL_2;
when "0001001" => SELECTED_SIGNAL_2(3 downto 0) <= SIGNAL_4_BIT_2_1;
SELECTED_SIGNAL_2(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_4_BIT_SAMPLE_CLK_2_1;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_4_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_4_BIT_SIGNAL_2;
when "0001010" => SELECTED_SIGNAL_2(3 downto 0) <= SIGNAL_4_BIT_2_2;
SELECTED_SIGNAL_2(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_4_BIT_SAMPLE_CLK_2_2;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_4_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_4_BIT_SIGNAL_2;
when "0001011" => SELECTED_SIGNAL_2(3 downto 0) <= SIGNAL_4_BIT_2_3;
SELECTED_SIGNAL_2(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_4_BIT_SAMPLE_CLK_2_3;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_4_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_4_BIT_SIGNAL_2;
when "0001100" => SELECTED_SIGNAL_2(3 downto 0) <= SIGNAL_4_BIT_2_4;
SELECTED_SIGNAL_2(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_4_BIT_SAMPLE_CLK_2_4;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_4_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_4_BIT_SIGNAL_2;
when "0001101" => SELECTED_SIGNAL_2(7 downto 0) <= SIGNAL_8_BIT_2_1;
SELECTED_SIGNAL_2(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_8_BIT_SAMPLE_CLK_2_1;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_8_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_8_BIT_SIGNAL_2;
when "0001110" => SELECTED_SIGNAL_2(7 downto 0) <= SIGNAL_8_BIT_2_2;
SELECTED_SIGNAL_2(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_8_BIT_SAMPLE_CLK_2_2;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_8_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_8_BIT_SIGNAL_2;
when "0001111" => SELECTED_SIGNAL_2(7 downto 0) <= SIGNAL_8_BIT_2_3;
SELECTED_SIGNAL_2(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_8_BIT_SAMPLE_CLK_2_3;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_8_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_8_BIT_SIGNAL_2;
when "0010000" => SELECTED_SIGNAL_2(7 downto 0) <= SIGNAL_8_BIT_2_4;
SELECTED_SIGNAL_2(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_8_BIT_SAMPLE_CLK_2_4;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_8_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_8_BIT_SIGNAL_2;
when "0010001" => SELECTED_SIGNAL_2 <= SIGNAL_16_BIT_2_1;
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_16_BIT_SAMPLE_CLK_2_1;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_16_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_16_BIT_SIGNAL_2;
when "0010010" => SELECTED_SIGNAL_2 <= SIGNAL_16_BIT_2_2;
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_16_BIT_SAMPLE_CLK_2_2;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_16_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_16_BIT_SIGNAL_2;
when "0010011" => SELECTED_SIGNAL_2 <= SIGNAL_16_BIT_2_3;
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_16_BIT_SAMPLE_CLK_2_3;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_16_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_16_BIT_SIGNAL_2;
when "0010100" => SELECTED_SIGNAL_2 <= SIGNAL_16_BIT_2_4;
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_16_BIT_SAMPLE_CLK_2_4;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_16_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_16_BIT_SIGNAL_2;
-- Add signals as necessary (up to 127 signals)
when others => SELECTED_SIGNAL_2 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= '0';
SELECTED_CAPTURED_SIGNAL_2 <= (others => '0');
SELECTED_STATE_2 <= "00";
end case;
end if;
end process;
-- Trace 3 input signal multiplexing
INPUT_MUX_TRACE3_001: process(ASYNC_RESET, CLK, REG244)
begin
if(ASYNC_RESET = '1') then
SELECTED_SIGNAL_3 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= '0';
SELECTED_CAPTURED_SIGNAL_3 <= (others => '0');
SELECTED_STATE_3 <= "00";
elsif rising_edge(CLK) then
case REG244(6 downto 0) is
-- Select one among the different signals to capture for trace 1
when "0000001" => SELECTED_SIGNAL_3(0) <= SIGNAL_1_BIT_3_1;
SELECTED_SIGNAL_3(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_1_BIT_SAMPLE_CLK_3_1;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_1_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_1_BIT_SIGNAL_3;
when "0000010" => SELECTED_SIGNAL_3(0) <= SIGNAL_1_BIT_3_2;
SELECTED_SIGNAL_3(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_1_BIT_SAMPLE_CLK_3_2;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_1_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_1_BIT_SIGNAL_3;
when "0000011" => SELECTED_SIGNAL_3(0) <= SIGNAL_1_BIT_3_3;
SELECTED_SIGNAL_3(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_1_BIT_SAMPLE_CLK_3_3;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_1_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_1_BIT_SIGNAL_3;
when "0000100" => SELECTED_SIGNAL_3(0) <= SIGNAL_1_BIT_3_4;
SELECTED_SIGNAL_3(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_1_BIT_SAMPLE_CLK_3_4;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_1_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_1_BIT_SIGNAL_3;
when "0000101" => SELECTED_SIGNAL_3(1 downto 0) <= SIGNAL_2_BIT_3_1;
SELECTED_SIGNAL_3(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_2_BIT_SAMPLE_CLK_3_1;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_2_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_2_BIT_SIGNAL_3;
when "0000110" => SELECTED_SIGNAL_3(1 downto 0) <= SIGNAL_2_BIT_3_2;
SELECTED_SIGNAL_3(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_2_BIT_SAMPLE_CLK_3_2;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_2_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_2_BIT_SIGNAL_3;
when "0000111" => SELECTED_SIGNAL_3(1 downto 0) <= SIGNAL_2_BIT_3_3;
SELECTED_SIGNAL_3(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_2_BIT_SAMPLE_CLK_3_3;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_2_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_2_BIT_SIGNAL_3;
when "0001000" => SELECTED_SIGNAL_3(1 downto 0) <= SIGNAL_2_BIT_3_4;
SELECTED_SIGNAL_3(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_2_BIT_SAMPLE_CLK_3_4;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_2_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_2_BIT_SIGNAL_3;
when "0001001" => SELECTED_SIGNAL_3(3 downto 0) <= SIGNAL_4_BIT_3_1;
SELECTED_SIGNAL_3(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_4_BIT_SAMPLE_CLK_3_1;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_4_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_4_BIT_SIGNAL_3;
when "0001010" => SELECTED_SIGNAL_3(3 downto 0) <= SIGNAL_4_BIT_3_2;
SELECTED_SIGNAL_3(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_4_BIT_SAMPLE_CLK_3_2;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_4_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_4_BIT_SIGNAL_3;
when "0001011" => SELECTED_SIGNAL_3(3 downto 0) <= SIGNAL_4_BIT_3_3;
SELECTED_SIGNAL_3(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_4_BIT_SAMPLE_CLK_3_3;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_4_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_4_BIT_SIGNAL_3;
when "0001100" => SELECTED_SIGNAL_3(3 downto 0) <= SIGNAL_4_BIT_3_4;
SELECTED_SIGNAL_3(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_4_BIT_SAMPLE_CLK_3_4;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_4_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_4_BIT_SIGNAL_3;
when "0001101" => SELECTED_SIGNAL_3(7 downto 0) <= SIGNAL_8_BIT_3_1;
SELECTED_SIGNAL_3(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_8_BIT_SAMPLE_CLK_3_1;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_8_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_8_BIT_SIGNAL_3;
when "0001110" => SELECTED_SIGNAL_3(7 downto 0) <= SIGNAL_8_BIT_3_2;
SELECTED_SIGNAL_3(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_8_BIT_SAMPLE_CLK_3_2;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_8_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_8_BIT_SIGNAL_3;
when "0001111" => SELECTED_SIGNAL_3(7 downto 0) <= SIGNAL_8_BIT_3_3;
SELECTED_SIGNAL_3(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_8_BIT_SAMPLE_CLK_3_3;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_8_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_8_BIT_SIGNAL_3;
when "0010000" => SELECTED_SIGNAL_3(7 downto 0) <= SIGNAL_8_BIT_3_4;
SELECTED_SIGNAL_3(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_8_BIT_SAMPLE_CLK_3_4;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_8_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_8_BIT_SIGNAL_3;
when "0010001" => SELECTED_SIGNAL_3 <= SIGNAL_16_BIT_3_1;
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_16_BIT_SAMPLE_CLK_3_1;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_16_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_16_BIT_SIGNAL_3;
when "0010010" => SELECTED_SIGNAL_3 <= SIGNAL_16_BIT_3_2;
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_16_BIT_SAMPLE_CLK_3_2;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_16_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_16_BIT_SIGNAL_3;
when "0010011" => SELECTED_SIGNAL_3 <= SIGNAL_16_BIT_3_3;
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_16_BIT_SAMPLE_CLK_3_3;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_16_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_16_BIT_SIGNAL_3;
when "0010100" => SELECTED_SIGNAL_3 <= SIGNAL_16_BIT_3_4;
SELECTED_SIGNAL_SAMPLE_CLK_3 <= SIGNAL_16_BIT_SAMPLE_CLK_3_4;
SELECTED_CAPTURED_SIGNAL_3 <= CAPTURED_16_BIT_SIGNAL_3;
SELECTED_STATE_3 <= STATE_16_BIT_SIGNAL_3;
-- Add signals as necessary (up to 127 signals)
when others => SELECTED_SIGNAL_3 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_3 <= '0';
SELECTED_CAPTURED_SIGNAL_3 <= (others => '0');
SELECTED_STATE_3 <= "00";
end case;
end if;
end process;
-- Trace 4 input signal multiplexing
INPUT_MUX_TRACE4_001: process(ASYNC_RESET, CLK, REG246)
begin
if(ASYNC_RESET = '1') then
SELECTED_SIGNAL_4 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= '0';
SELECTED_CAPTURED_SIGNAL_4 <= (others => '0');
SELECTED_STATE_4 <= "00";
elsif rising_edge(CLK) then
case REG246(6 downto 0) is
-- Select one among the different signals to capture for trace 1
when "0000001" => SELECTED_SIGNAL_4(0) <= SIGNAL_1_BIT_4_1;
SELECTED_SIGNAL_4(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_1_BIT_SAMPLE_CLK_4_1;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_1_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_1_BIT_SIGNAL_4;
when "0000010" => SELECTED_SIGNAL_4(0) <= SIGNAL_1_BIT_4_2;
SELECTED_SIGNAL_4(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_1_BIT_SAMPLE_CLK_4_2;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_1_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_1_BIT_SIGNAL_4;
when "0000011" => SELECTED_SIGNAL_4(0) <= SIGNAL_1_BIT_4_3;
SELECTED_SIGNAL_4(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_1_BIT_SAMPLE_CLK_4_3;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_1_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_1_BIT_SIGNAL_4;
when "0000100" => SELECTED_SIGNAL_4(0) <= SIGNAL_1_BIT_4_4;
SELECTED_SIGNAL_4(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_1_BIT_SAMPLE_CLK_4_4;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_1_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_1_BIT_SIGNAL_4;
when "0000101" => SELECTED_SIGNAL_4(1 downto 0) <= SIGNAL_2_BIT_4_1;
SELECTED_SIGNAL_4(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_2_BIT_SAMPLE_CLK_4_1;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_2_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_2_BIT_SIGNAL_4;
when "0000110" => SELECTED_SIGNAL_4(1 downto 0) <= SIGNAL_2_BIT_4_2;
SELECTED_SIGNAL_4(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_2_BIT_SAMPLE_CLK_4_2;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_2_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_2_BIT_SIGNAL_4;
when "0000111" => SELECTED_SIGNAL_4(1 downto 0) <= SIGNAL_2_BIT_4_3;
SELECTED_SIGNAL_4(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_2_BIT_SAMPLE_CLK_4_3;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_2_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_2_BIT_SIGNAL_4;
when "0001000" => SELECTED_SIGNAL_4(1 downto 0) <= SIGNAL_2_BIT_4_4;
SELECTED_SIGNAL_4(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_2_BIT_SAMPLE_CLK_4_4;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_2_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_2_BIT_SIGNAL_4;
when "0001001" => SELECTED_SIGNAL_4(3 downto 0) <= SIGNAL_4_BIT_4_1;
SELECTED_SIGNAL_4(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_4_BIT_SAMPLE_CLK_4_1;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_4_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_4_BIT_SIGNAL_4;
when "0001010" => SELECTED_SIGNAL_4(3 downto 0) <= SIGNAL_4_BIT_4_2;
SELECTED_SIGNAL_4(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_4_BIT_SAMPLE_CLK_4_2;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_4_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_4_BIT_SIGNAL_4;
when "0001011" => SELECTED_SIGNAL_4(3 downto 0) <= SIGNAL_4_BIT_4_3;
SELECTED_SIGNAL_4(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_4_BIT_SAMPLE_CLK_4_3;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_4_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_4_BIT_SIGNAL_4;
when "0001100" => SELECTED_SIGNAL_4(3 downto 0) <= SIGNAL_4_BIT_4_4;
SELECTED_SIGNAL_4(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_4_BIT_SAMPLE_CLK_4_4;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_4_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_4_BIT_SIGNAL_4;
when "0001101" => SELECTED_SIGNAL_4(7 downto 0) <= SIGNAL_8_BIT_4_1;
SELECTED_SIGNAL_4(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_8_BIT_SAMPLE_CLK_4_1;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_8_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_8_BIT_SIGNAL_4;
when "0001110" => SELECTED_SIGNAL_4(7 downto 0) <= SIGNAL_8_BIT_4_2;
SELECTED_SIGNAL_4(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_8_BIT_SAMPLE_CLK_4_2;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_8_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_8_BIT_SIGNAL_4;
when "0001111" => SELECTED_SIGNAL_4(7 downto 0) <= SIGNAL_8_BIT_4_3;
SELECTED_SIGNAL_4(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_8_BIT_SAMPLE_CLK_4_3;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_8_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_8_BIT_SIGNAL_4;
when "0010000" => SELECTED_SIGNAL_4(7 downto 0) <= SIGNAL_8_BIT_4_4;
SELECTED_SIGNAL_4(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_8_BIT_SAMPLE_CLK_4_4;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_8_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_8_BIT_SIGNAL_4;
when "0010001" => SELECTED_SIGNAL_4 <= SIGNAL_16_BIT_4_1;
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_16_BIT_SAMPLE_CLK_4_1;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_16_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_16_BIT_SIGNAL_4;
when "0010010" => SELECTED_SIGNAL_4 <= SIGNAL_16_BIT_4_2;
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_16_BIT_SAMPLE_CLK_4_2;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_16_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_16_BIT_SIGNAL_4;
when "0010011" => SELECTED_SIGNAL_4 <= SIGNAL_16_BIT_4_3;
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_16_BIT_SAMPLE_CLK_4_3;
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