?? comscope.vhd
字號:
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-- Filename: COMSCOPE.VHD
-- Author: Alain Zarembowitch / MSS
-- Version: 2
-- Date last modified: 9-08-03
-- Inheritance: none
--
--
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COMSCOPE is port (
--GLOBAL CLOCKS
CLK : in std_logic; -- Master clock for this FPGA
ASYNC_RESET: in std_logic; -- Asynchronous reset active high
-- Choose between signed or unsigned representation
SIGNED_REPRESENTATION_U_SIGNED_N: in std_logic;
-- '0' Unsigned
-- '1' Signed
-- Input registers
REG237: in std_logic_vector(7 downto 0);
REG238: in std_logic_vector(7 downto 0);
REG239: in std_logic_vector(7 downto 0);
REG240: in std_logic_vector(7 downto 0);
REG241: in std_logic_vector(7 downto 0);
REG242: in std_logic_vector(7 downto 0);
REG243: in std_logic_vector(7 downto 0);
REG244: in std_logic_vector(7 downto 0);
REG245: in std_logic_vector(7 downto 0);
REG246: in std_logic_vector(7 downto 0);
REG247: in std_logic_vector(7 downto 0);
REG248: in std_logic_vector(7 downto 0);
REG249: in std_logic_vector(7 downto 0);
-- Trace 1 input signals
-- 1-bit signals
SIGNAL_1_BIT_1_1: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_1_1: in std_logic;
SIGNAL_1_BIT_1_2: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_1_2: in std_logic;
SIGNAL_1_BIT_1_3: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_1_3: in std_logic;
SIGNAL_1_BIT_1_4: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_1_4: in std_logic;
-- 2-bit signals
SIGNAL_2_BIT_1_1: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_1_1: in std_logic;
SIGNAL_2_BIT_1_2: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_1_2: in std_logic;
SIGNAL_2_BIT_1_3: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_1_3: in std_logic;
SIGNAL_2_BIT_1_4: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_1_4: in std_logic;
-- 4-bit signals
SIGNAL_4_BIT_1_1: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_1_1: in std_logic;
SIGNAL_4_BIT_1_2: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_1_2: in std_logic;
SIGNAL_4_BIT_1_3: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_1_3: in std_logic;
SIGNAL_4_BIT_1_4: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_1_4: in std_logic;
-- 8-bit signals
SIGNAL_8_BIT_1_1: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_1_1: in std_logic;
SIGNAL_8_BIT_1_2: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_1_2: in std_logic;
SIGNAL_8_BIT_1_3: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_1_3: in std_logic;
SIGNAL_8_BIT_1_4: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_1_4: in std_logic;
-- 16-bit signals
SIGNAL_16_BIT_1_1: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_1_1: in std_logic;
SIGNAL_16_BIT_1_2: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_1_2: in std_logic;
SIGNAL_16_BIT_1_3: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_1_3: in std_logic;
SIGNAL_16_BIT_1_4: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_1_4: in std_logic;
-- Add signals as necessary (up to 127 signals total per trace)
-- Trace 2 input signals
-- 1-bit signals
SIGNAL_1_BIT_2_1: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_2_1: in std_logic;
SIGNAL_1_BIT_2_2: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_2_2: in std_logic;
SIGNAL_1_BIT_2_3: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_2_3: in std_logic;
SIGNAL_1_BIT_2_4: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_2_4: in std_logic;
-- 2-bit signals
SIGNAL_2_BIT_2_1: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_2_1: in std_logic;
SIGNAL_2_BIT_2_2: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_2_2: in std_logic;
SIGNAL_2_BIT_2_3: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_2_3: in std_logic;
SIGNAL_2_BIT_2_4: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_2_4: in std_logic;
-- 4-bit signals
SIGNAL_4_BIT_2_1: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_2_1: in std_logic;
SIGNAL_4_BIT_2_2: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_2_2: in std_logic;
SIGNAL_4_BIT_2_3: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_2_3: in std_logic;
SIGNAL_4_BIT_2_4: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_2_4: in std_logic;
-- 8-bit signals
SIGNAL_8_BIT_2_1: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_2_1: in std_logic;
SIGNAL_8_BIT_2_2: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_2_2: in std_logic;
SIGNAL_8_BIT_2_3: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_2_3: in std_logic;
SIGNAL_8_BIT_2_4: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_2_4: in std_logic;
-- 16-bit signals
SIGNAL_16_BIT_2_1: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_2_1: in std_logic;
SIGNAL_16_BIT_2_2: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_2_2: in std_logic;
SIGNAL_16_BIT_2_3: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_2_3: in std_logic;
SIGNAL_16_BIT_2_4: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_2_4: in std_logic;
-- Add signals as necessary (up to 127 signals total per trace)
-- Trace 3 input signals
-- 1-bit signals
SIGNAL_1_BIT_3_1: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_3_1: in std_logic;
SIGNAL_1_BIT_3_2: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_3_2: in std_logic;
SIGNAL_1_BIT_3_3: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_3_3: in std_logic;
SIGNAL_1_BIT_3_4: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_3_4: in std_logic;
-- 2-bit signals
SIGNAL_2_BIT_3_1: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_3_1: in std_logic;
SIGNAL_2_BIT_3_2: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_3_2: in std_logic;
SIGNAL_2_BIT_3_3: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_3_3: in std_logic;
SIGNAL_2_BIT_3_4: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_3_4: in std_logic;
-- 4-bit signals
SIGNAL_4_BIT_3_1: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_3_1: in std_logic;
SIGNAL_4_BIT_3_2: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_3_2: in std_logic;
SIGNAL_4_BIT_3_3: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_3_3: in std_logic;
SIGNAL_4_BIT_3_4: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_3_4: in std_logic;
-- 8-bit signals
SIGNAL_8_BIT_3_1: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_3_1: in std_logic;
SIGNAL_8_BIT_3_2: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_3_2: in std_logic;
SIGNAL_8_BIT_3_3: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_3_3: in std_logic;
SIGNAL_8_BIT_3_4: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_3_4: in std_logic;
-- 16-bit signals
SIGNAL_16_BIT_3_1: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_3_1: in std_logic;
SIGNAL_16_BIT_3_2: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_3_2: in std_logic;
SIGNAL_16_BIT_3_3: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_3_3: in std_logic;
SIGNAL_16_BIT_3_4: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_3_4: in std_logic;
-- Add signals as necessary (up to 127 signals total per trace)
-- Trace 4 input signals
-- 1-bit signals
SIGNAL_1_BIT_4_1: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_4_1: in std_logic;
SIGNAL_1_BIT_4_2: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_4_2: in std_logic;
SIGNAL_1_BIT_4_3: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_4_3: in std_logic;
SIGNAL_1_BIT_4_4: in std_logic;
SIGNAL_1_BIT_SAMPLE_CLK_4_4: in std_logic;
-- 2-bit signals
SIGNAL_2_BIT_4_1: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_4_1: in std_logic;
SIGNAL_2_BIT_4_2: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_4_2: in std_logic;
SIGNAL_2_BIT_4_3: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_4_3: in std_logic;
SIGNAL_2_BIT_4_4: in std_logic_vector(1 downto 0);
SIGNAL_2_BIT_SAMPLE_CLK_4_4: in std_logic;
-- 4-bit signals
SIGNAL_4_BIT_4_1: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_4_1: in std_logic;
SIGNAL_4_BIT_4_2: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_4_2: in std_logic;
SIGNAL_4_BIT_4_3: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_4_3: in std_logic;
SIGNAL_4_BIT_4_4: in std_logic_vector(3 downto 0);
SIGNAL_4_BIT_SAMPLE_CLK_4_4: in std_logic;
-- 8-bit signals
SIGNAL_8_BIT_4_1: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_4_1: in std_logic;
SIGNAL_8_BIT_4_2: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_4_2: in std_logic;
SIGNAL_8_BIT_4_3: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_4_3: in std_logic;
SIGNAL_8_BIT_4_4: in std_logic_vector(7 downto 0);
SIGNAL_8_BIT_SAMPLE_CLK_4_4: in std_logic;
-- 16-bit signals
SIGNAL_16_BIT_4_1: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_4_1: in std_logic;
SIGNAL_16_BIT_4_2: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_4_2: in std_logic;
SIGNAL_16_BIT_4_3: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_4_3: in std_logic;
SIGNAL_16_BIT_4_4: in std_logic_vector(15 downto 0);
SIGNAL_16_BIT_SAMPLE_CLK_4_4: in std_logic;
-- Add signals as necessary (up to 127 signals total per trace)
-- Trigger signals
-- 1-bit Triggers
TRIGGER_1_BIT_1: in std_logic;
TRIGGER_1_BIT_SAMPLE_CLK_1: in std_logic;
TRIGGER_1_BIT_2: in std_logic;
TRIGGER_1_BIT_SAMPLE_CLK_2: in std_logic;
TRIGGER_1_BIT_3: in std_logic;
TRIGGER_1_BIT_SAMPLE_CLK_3: in std_logic;
TRIGGER_1_BIT_4: in std_logic;
TRIGGER_1_BIT_SAMPLE_CLK_4: in std_logic;
-- 2-bit Triggers
TRIGGER_2_BIT_1: in std_logic_vector(1 downto 0);
TRIGGER_2_BIT_SAMPLE_CLK_1: in std_logic;
TRIGGER_2_BIT_2: in std_logic_vector(1 downto 0);
TRIGGER_2_BIT_SAMPLE_CLK_2: in std_logic;
TRIGGER_2_BIT_3: in std_logic_vector(1 downto 0);
TRIGGER_2_BIT_SAMPLE_CLK_3: in std_logic;
TRIGGER_2_BIT_4: in std_logic_vector(1 downto 0);
TRIGGER_2_BIT_SAMPLE_CLK_4: in std_logic;
-- 4-bit Triggers
TRIGGER_4_BIT_1: in std_logic_vector(3 downto 0);
TRIGGER_4_BIT_SAMPLE_CLK_1: in std_logic;
TRIGGER_4_BIT_2: in std_logic_vector(3 downto 0);
TRIGGER_4_BIT_SAMPLE_CLK_2: in std_logic;
TRIGGER_4_BIT_3: in std_logic_vector(3 downto 0);
TRIGGER_4_BIT_SAMPLE_CLK_3: in std_logic;
TRIGGER_4_BIT_4: in std_logic_vector(3 downto 0);
TRIGGER_4_BIT_SAMPLE_CLK_4: in std_logic;
-- 8-bit Triggers
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