/**
 *  @file ftmcp100.h
 *  @brief This file consists of various kind of definitions for ftmcp100 media 
 *         coprocessor architecture.
 *
 */
#ifndef FTMCP100_H
#define FTMCP100_H

//---------------------------------------------------------------------------
/*****************************************************************************
 *  Platform Options and Settings
 ****************************************************************************/
/**
 * Since there are different kind of hardware versions, so we define following flag 
 * here to distinguish between various kind of hardware core.
 *
 *  We put these flags in project setting instead inside the program body. Well,just
 *  write these flags here for the purpose of reminder and explanation.
 *  Don't define these flags inside program. Define them in project settings.
 *
 *  #define CORE_VERSION_1
 *  #define CORE_VERSION_2
 *  #define FIE8120
 *
 *  Well, basically the 'FIE8120_TARGET' target belongs to CORE_VERSION_2 with some differences
 *  listed below :
 *    - For FIE8120_TARGET, just like CORE_VERSION_1 , the field 
 *     'Local Memory Base Address' in DMA's 'Local Memory Base Address Register' 
 *      register is still one word address instead of 2 words addresses. Hence,we 
 *      don't have to use TRANSLATE_LOCAL_MEMORY_BASE_ADDRESS() macro.
 *    - For FIE8120_TARGET, since there is no embedded CPU like CORE_VERSION_2, so we
 *      we must make base address offset similar to CORE_VERSION_1.
 *
 */
#if (!defined(CORE_VERSION_1) && !defined(CORE_VERSION_2))
  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"
#endif

//---------------------------------------------------------------------------
/**
 *  Our MPEG4 encoder will run on both RTL platform and FPGA platform. For 
 *  the purpose of one unified single MPEG4 firmware code, we integrate the 
 *  codes on both platforms together and define two flags to decide the platform.
 *  But these two flags will be defined in project setting instead within code 
 *  body. We just write these flags here for the purpose of reminder.
 *  Don't define these two flags in program. Define them in project settings.
 *  #define FPGA_PLATFROM
 *  #define RTL_PLATFORM
 */
#if defined(FPGA_PLATFORM)
    //#define DUMP_RECONSTRUCTED_RESULT /**< To instrcut the MPEG4 encoder to dump 
    //                                   *   the result of reconstructed image.
    //                                   */
                             
    //#define DUMP_ME_RESULT  /**< This flag was used for debug purpose -- mainly
    //                         *   used for dumping the ME result to file under
    //                         *   FPGA platform
    //                         */
                             
    //#define DUMP_PMV_RESULT /**< This flag was used for debug purpose -- mainly
    //                         *   used for dumping the PMV to file under
    //                         *   FPGA platform
    //                         */  
    
    //#define DUMP_WITH_RADDR  /**< to dump the raddr setting together while 
    //                          *   DUMP_PMV_RESULT flag is enabled
    //                          */  
    
#elif defined(RTL_PLATFORM)

#else
  #error "Please define the platfrom flags in project setting (either FPGA_PLATFORM or RTL_PLATFORM)"
#endif
//---------------------------------------------------------------------------
#ifdef CORE_VERSION_1
  #define ME_COMMAND_QUEUE_ADDR     0x200
  #define DMA_COMMAND_LOCAL_ADDR    0x480
  #define INTRA_QUANT_TABLE_ADDR    0x7C00
  #define INTER_QUANT_TABLE_ADDR    0x7D00
#elif defined(CORE_VERSION_2)
  #ifdef FIE8120
    #define ME_COMMAND_QUEUE_ADDR     0x200
    #define DMA_COMMAND_LOCAL_ADDR    0x480
    #define INTRA_QUANT_TABLE_ADDR    0x7C00
    #define INTER_QUANT_TABLE_ADDR    0x7D00  
  #else
    #define ME_COMMAND_QUEUE_ADDR     0x10200
    #define DMA_COMMAND_LOCAL_ADDR    0x10480
    #define INTRA_QUANT_TABLE_ADDR    0x17C00
    #define INTER_QUANT_TABLE_ADDR    0x17D00
  #endif
#else
  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"
#endif

#ifdef FIE8120
  #define TRANSLATE_LOCAL_MEMORY_BASE_ADDRESS(v) ((uint32_t)v)
#else
  #define TRANSLATE_LOCAL_MEMORY_BASE_ADDRESS(v) ( (((((uint32_t)v)|0x10000)>>1)&0x0fffffffc) | (((uint32_t)v)&0x03) )
#endif
#define DZQAR					    0x8000800
#define stride_MB				    384
#define DMA_COMMAND_QUEUE_STRIDE    48
//---------------------------------------------------------------------------
/*****************************************************************************
 *  DMA move things
 ****************************************************************************/
#if defined(CORE_VERSION_1)
  // For hardware code version 1, the DMA chain commands must move from
  // local memory to system memory and start the DMA mechanism directly
  // from system memory.
  #define DMA_MOVE(v1, v2) \
	pmdma->Status = 0; \
	pmdma->SMaddr = pCodec->DMA_COMMAND_system_phy; \
	pmdma->LMaddr = (DMA_COMMAND_LOCAL_ADDR+(v1<<2)); \
	pmdma->BlkWidth = 0; \
	pmdma->CCA = (uint32_t) pCodec->DMA_COMMAND_system_phy; \
	pmdma->Control = v2;
	
#elif defined(CORE_VERSION_2)
  // For hardware code version 2, hardware code has improved and allows DMA 
  // chain commands to start the DMA mechansim directly from local memory 
  // without moving to system memory like hardware code version 1. So we
  // modify the code and allow it to start the DMA procedure directly from
  // local memory.
  // make the transfer length to 0 , and specify command source as local memory

//  #define DMA_MOVE(v1, v2)\
//    pmdma->Status = 0;\
//    pmdma->CCA = (uint32_t)(DMA_COMMAND_LOCAL_ADDR+(v1<<2))| 0x02;\
//    pmdma->Control =(uint32_t) 0x04A00000;
  #define DMA_MOVE(v1, v2) pmdma->Status = 0;  pmdma->CCA = (uint32_t)(DMA_COMMAND_LOCAL_ADDR+(v1<<2))| 0x02;  pmdma->Control =(uint32_t) 0x04A00000;
  
#else
  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"
#endif
//---------------------------------------------------------------------------

  typedef struct MP4Tag {
    uint32_t MECTL;
    uint32_t MEPMV;
    uint32_t MECR;
    uint32_t MIN_SADMV;
    uint32_t CMDADDR;
    uint32_t MECADDR;
    uint32_t HOFFSET;
    uint32_t MCCTL;
    uint32_t MCCADDR;
    uint32_t MEIADDR;
    uint32_t CPSTS;
    uint32_t QCR_0;
    uint32_t QCR_1;
    uint32_t QCR_2;
    uint32_t QAR;
    uint32_t CKR;
    uint32_t ACDCPAR;
    uint32_t VOADR;
    uint32_t CURDEV;
    uint32_t BADR;
    uint32_t BALR;
    uint32_t MVXYD;
    uint32_t MCIADDR;
    uint32_t VLDCTL;
    uint32_t VOP0;
    uint32_t VOP1;
    uint32_t SCODE;
    uint32_t RSMRK;
    uint32_t TOADR;
    uint32_t VLDSTS;
    uint32_t ASADR;
    uint32_t INTEN;
    uint32_t VOPSIZE;
    uint32_t PMVBUF;
  } MP4_t;
  
  #define DECLARE_MP4_PTR volatile MP4_t *ptMP4 = (MP4_t *)(pCodec->pCoreBaseAddr + MP4_OFFSET);
  
  #ifdef CORE_VERSION_1
    #define MP4_OFFSET  0x10000
	#define MDMA1 ((volatile MDMA *)( 0x10400 + pCodec->pCoreBaseAddr))
  #elif defined(CORE_VERSION_2)
    #ifdef FIE8120
      #define MP4_OFFSET  0x10000
	  #define MDMA1 ((volatile MDMA *)( 0x10400 + pCodec->pCoreBaseAddr))
    #else
      #define MP4_OFFSET  0x20000
      #define MDMA1 ((volatile MDMA *)( 0x20400 + pCodec->pCoreBaseAddr))
    #endif
  #else  
    #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"    
  #endif
  
    #define READ_CPSTS(v) 		v=ptMP4->CPSTS;		// coprocessor status register
	#define READ_VOADR(v)		v=ptMP4->VOADR;
	#define READ_MIN_SADMV(v) 	v=ptMP4->MIN_SADMV;
	#define READ_CURDEV(v) 		v=ptMP4->CURDEV;
	#define READ_BALR(v) 		v=ptMP4->BALR;
	#define READ_VOP0(v)        v=ptMP4->VOP0;
	#define READ_VLDSTS(v) 		v=ptMP4->VLDSTS;
	#define READ_ASADR(v) 		v=ptMP4->ASADR;
	
	#define SET_BADR(v)		    ptMP4->BADR=v;	
	#define SET_BALR(v)			ptMP4->BALR=v;
	#define SET_MCCADDR(v) 		ptMP4->MCCADDR=v; // MC current block start address register
	#define SET_QAR(v) 			ptMP4->QAR=v; // Quantization block address register
	#define SET_CKR(v) 			ptMP4->CKR=v;
	#define SET_MEIADDR(v) 		ptMP4->MEIADDR=v; // ME interpolation block start address register
	#define SET_CMDADDR(v) 		ptMP4->CMDADDR=v;
	#define SET_MECADDR(v) 		ptMP4->MECADDR=v; // ME current block start address register
	#define SET_ACDCPAR(v) 		ptMP4->ACDCPAR=v; // ACDC Predictor Buffer Address Register
	#define SET_VOADR(v) 		ptMP4->VOADR=v;
	#define SET_MCIADDR(v) 		ptMP4->MCIADDR=v;
	#define SET_QCR_0(v) 		ptMP4->QCR_0=v;
	#define SET_QCR_1(v) 		ptMP4->QCR_1=v;
	#define SET_QCR_2(v)	 	ptMP4->QCR_2=v;
	#define SET_MCCTL(v) 		ptMP4->MCCTL=v;
	#define SET_HOFFSET(v) 		ptMP4->HOFFSET=v; // Horizontal offset to reference block address
	#define SET_MECR(v)			ptMP4->MECR=v;
	#define SET_MEPMV(v) 		ptMP4->MEPMV=v;
	#define SET_MECTL(v) 		ptMP4->MECTL=v;	  // ME Control Register
	#define SET_VLDCTL(v) 		ptMP4->VLDCTL=v;
	#define SET_VOP0(v)         ptMP4->VOP0=v;
	#define SET_ASADR(v) 		ptMP4->ASADR=v;
	
    #define SET_MVXYD(v)        ptMP4->MVXYD=v;
	#define SET_VOPSIZE(v) 		ptMP4->VOPSIZE=v;
	#define SET_PMVBUF(v) 		ptMP4->PMVBUF=v;
  
/*	
  #ifdef CORE_VERSION_1
	#define MDMA1 ((volatile MDMA *)( 0x10400 + pCodec->pCoreBaseAddr))

	#define MECTL       (0x10000 + pCodec->pCoreBaseAddr)
	#define MEPMV       (0x10004 + pCodec->pCoreBaseAddr)
	#define MECR        (0x10008 + pCodec->pCoreBaseAddr)
	#define MIN_SADMV   (0x1000c + pCodec->pCoreBaseAddr)
	#define CMDADDR     (0x10010 + pCodec->pCoreBaseAddr)
	#define MECADDR     (0x10014 + pCodec->pCoreBaseAddr)
	#define HOFFSET     (0x10018 + pCodec->pCoreBaseAddr)
	#define MCCTL       (0x1001c + pCodec->pCoreBaseAddr)