#ifndef FTMCP100_H#define FTMCP100_H//---------------------------------------------------------------------------//  Platform Options and Settings//---------------------------------------------------------------------------/** * Since there are different kind of hardware versions, so we define following flag  * here to distinguish between various kind of hardware core. */#define CORE_VERSION_1//#define CORE_VERSION_2#if (!defined(CORE_VERSION_1) && !defined(CORE_VERSION_2))  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif/** *  The JPEG decoder will run on both RTL platform and FPGA platform. For  *  the purpose of one unified single JPEG decoder firmware code, we integrate the  *  codes on both platforms together and define two flags to decide the platform. *  But these two flags will be defined in project setting instead within code  *  body. We just write these flags here for the purpose of reminder. *  Don't define these two flags in program. Define them in project settings. *///#define FPGA_PLATFORM//#define RTL_PLATFORM#if (!defined(FPGA_PLATFORM) && !defined(RTL_PLATFORM))  #error "Please define the the target platform  (either FPGA_PLATFORM or RTL_PLATFORM)"#endif//---------------------------------------------------------------------------//  Platform Options and Settings//---------------------------------------------------------------------------/** *  Various kind of #define constants for compiler preprocessor configuration setting of  *  FTMCP100 media coprocessor. */ // added by Leo for various output controls#ifdef RTL_PLATFORM  #define VPE_OUTPUT  //#define VPE_DUMP_YUV // to enalbe the dumping of YUV data (mp4.yuv file in RTL simulation)#endif#ifdef CORE_VERSION_2  // In core_version_2 , we can use the auto-increment mechanism for DMA engine, so we set   // the following flag to tell the performance difference.  #define USING_AUTO_INCREMNET#endif//---------------------------------------------------------------------------//---------------------------------------------------------------------------/** *  Various kind of #define constants mainly used for FTMCP100 media coprocessor. */#define CKR_RATIO 0#define VPE 		0x90180000#define RTL_DEBUG_OUT(v) *(unsigned int*)VPE=v;/*#ifdef CORE_VERSION_1  #ifdef FPGA_PLATFORM    #define BASE_ADDRESS		0x90700000 // used for Test Chip FIE8100    #elif defined(RTL_PLATFORM)    #define BASE_ADDRESS		0x90700000 // used for RTL simulation  #else    #error "Please define the platfrom flags in project setting (either FPGA_PLATFORM or RTL_PLATFORM)"  #endif	#elif defined(CORE_VERSION_2)  #ifdef FPGA_PLATFORM    #define BASE_ADDRESS		0x90e10000 // used for newer hardware core  #elif defined(RTL_PLATFORM)    #define BASE_ADDRESS		0x90710000 // used for RTL simulation  #else    #error "Please define the platfrom flags in project setting (either FPGA_PLATFORM or RTL_PLATFORM)"  #endif#else  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif*/typedef struct {  #ifdef CORE_VERSION_1    // 10 blocks at most.. and each DMA command set occupies 4 words    // so the allocated space requires 4*10*sizeof(unsigned int)    // the system DMA memory space under CORE_VERSION_1 architecture    // the allocated system DMA memory space requires 4-byte alignment.    unsigned int *pSDMA_virt;    unsigned int *pSDMA_phy;  #endif  unsigned char *pCoreBaseAddr;  void * pfnDmaMalloc; // The function pointer to user-defined DMA memory allocation function.    void * pfnDmaFree; // The function pointer to user-defined DMA free allocation function.    unsigned char *outdata[3]; // the output YUV 8-byte aligned buffer (pyhsical address)    // ping pong buffer between VLD-DZ Engine and DQ-MC Engine  //0000 --- 0400 --- 0800 (10 bolcks + 10 blocks)  // since DZAR and QAR require 1KB aligned  unsigned short *pingpong_buf[2];    unsigned int *pLDMA; // DMA command buffer's begin address in local memory  int buf_descriptor1; // used to select ping pong buffer for VLD output  int buf_descriptor2; // used to select buffer between DQ-MC stage and DMA stage (indicated by MCIADDR for DQ-MC engine output)      #ifdef USE_INTERNAL_CPU        unsigned int *pLDMA_INTERNAL_CPU; // DMA command buffer's begin address in local memory                              // for moving internal CPU code to embedded CPU  #endif  } FTMCP100_CODEC;//---------------------------------------------------------------------------//---------------------------------------------------------------------------//--------------- Bank0 ---------------------//#ifdef CORE_VERSION_1  // ping pong buffer between VLD-DZ Engine and DQ-MC Engine  //0000 --- 0400 --- 0800 (10 bolcks + 10 blocks)  // since DZAR and QAR require 1KB aligned  #define PINGPONG_BUFFER_0_ADDR  0x000  #define PINGPONG_BUFFER_1_ADDR  0x800  // DMA_command  #define DMA_COMMAND_LOCAL_ADDR  0x0d00#elif defined(CORE_VERSION_2)  // ping pong buffer between VLD-DZ Engine and DQ-MC Engine  //0000 --- 0400 --- 0800 (10 bolcks + 10 blocks)  // since DZAR and QAR require 1KB aligned  #define PINGPONG_BUFFER_0_ADDR  0x10000  #define PINGPONG_BUFFER_1_ADDR  0x10800  // DMA_command  #define DMA_COMMAND_LOCAL_ADDR  0x10d00#else  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif#ifdef USE_INTERNAL_CPU  #define DMA_COMMAND_INTERNAL_CPU  0x10f00#endif// vld input buffer for hardware's autobuffer#define VLD_AUTOBUFFER_ADDR 0x500#ifdef CORE_VERSION_2  #define TRANSLATE_LOCAL_MEMORY_BASE_ADDRESS(v) ( (((((unsigned int)v)|0x10000)>>1)&0x0fffffffc) | (((unsigned int)v)&0x03) )  #endif//--------------- Bank1 ---------------------//// storing the pointer of each block in MCU (double buffer)#define CUR_B0  (0x4000)      //4000 -- 4280#define CUR_B1  (0x4040)      //4000 -- 4280#define CUR_B2  (0x4080)      //4000 -- 4280#define CUR_B3  (0x40c0)      //4000 -- 4280#define CUR_B4  (0x4100)      //4000 -- 4280#define CUR_B5  (0x4140)      //4000 -- 4280#define CUR_B6  (0x4180)      //4000 -- 4280#define CUR_B7  (0x41c0)      //4000 -- 4280#define CUR_B8  (0x4200)      //4000 -- 4280#define CUR_B9  (0x4240)      //4000 -- 4280// for double buffer's purpose#define STRIDE_MCU 0x280//--------------- Qtable ---------------------//// storing the qval and invqval in local mem (31k~32k)#ifdef CORE_VERSION_1  #define QTBL0  (0x7c00+pCodec->pCoreBaseAddr) //7c00 -- 7cff  #define QTBL1  (0x7d00+pCodec->pCoreBaseAddr) //7d00 -- 7dff  #define QTBL2  (0x7e00+pCodec->pCoreBaseAddr) //7e00 -- 7eff  #define QTBL3  (0x7f00+pCodec->pCoreBaseAddr) //7f00 -- 7fff#elif defined(CORE_VERSION_2)  #define QTBL0  (0x17c00+pCodec->pCoreBaseAddr) //7c00 -- 7cff  #define QTBL1  (0x17d00+pCodec->pCoreBaseAddr) //7d00 -- 7dff  #define QTBL2  (0x17e00+pCodec->pCoreBaseAddr) //7e00 -- 7eff  #define QTBL3  (0x17f00+pCodec->pCoreBaseAddr) //7f00 -- 7fff		    #else  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif//--------------- Bank2,3 ---------------------//// storing the huffman table in local mem (32k~36.5k)  // the smaller huffman table layout in local mem (32k~36.5k)  // Huffman AC Table 0 : 32K    ~ 34K     (0x8000~0x8800) (512 words, 1024 half-words)  // Huffman AC Table 1 : 34K    ~ 36K     (0x8800~0x9000) (512 words, 1024 half-words)     // Huffman DC Table 0 : 36K    ~ 36.25K  (0x9000~0x9100) (64  words, 128  half-words)  // Huffman DC Table 1 : 36.25K ~ 36.5K   (0x9100~0x9200) (64  words, 128  half-words)#ifdef CORE_VERSION_1  #define HUFTBL0_AC  (0x8000+pCodec->pCoreBaseAddr)	     //0x8000 -- 0x8800  #define HUFTBL1_AC  (0x8800+pCodec->pCoreBaseAddr)      //0x8800 -- 0x9000  #define HUFTBL0_DC  (0x9000+pCodec->pCoreBaseAddr)      //0x9000 -- 0x9100  #define HUFTBL1_DC  (0x9100+pCodec->pCoreBaseAddr)      //0x9100 -- 0x9200  #elif defined(CORE_VERSION_2)  #define HUFTBL0_AC  (0x18000+pCodec->pCoreBaseAddr)	     //0x8000 -- 0x8800  #define HUFTBL1_AC  (0x18800+pCodec->pCoreBaseAddr)      //0x8800 -- 0x9000  #define HUFTBL0_DC  (0x19000+pCodec->pCoreBaseAddr)      //0x9000 -- 0x9100  #define HUFTBL1_DC  (0x19100+pCodec->pCoreBaseAddr)      //0x9100 -- 0x9200#else  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif //---------------------------------------------///* added by Leo, zigzag coef order to natural and transposed order */extern const int jpeg_natural_transpozed_order[];//---------------------------------------------------------------------------// DMA Control Registers Structure Definition//---------------------------------------------------------------------------// well, using the strcutre to do register access is possibly platform specific// we improve it later once we are doing the abstraction of register access.#if defined(CORE_VERSION_1)  typedef struct {    unsigned int *SMaddr;    unsigned int *LMaddr;    unsigned int BlkWidth;    unsigned int Control;    unsigned int CCA;    unsigned int Status;  } MDMA;#elif defined(CORE_VERSION_2)  typedef struct {    unsigned int *SMaddr;    unsigned int *LMaddr;    unsigned int BlkWidth;    unsigned int Control;    unsigned int CCA;    unsigned int Status;    unsigned int CCA2;    unsigned int GRPC;    unsigned int GRPS;  } MDMA;#else  #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"#endif//---------------------------------------------------------------------------// Register definition//---------------------------------------------------------------------------	#ifdef CORE_VERSION_1	  #define MDMA1     ((volatile MDMA *)(0x10400 + pCodec->pCoreBaseAddr))	      #define MCUBR	    (0x10008 + pCodec->pCoreBaseAddr)      #define MECADDR   (0x10014 + pCodec->pCoreBaseAddr) // mainly used for setting debugging marker during RTL simulation , note that MECADDR[3:0] is ignored      #define MCCTL     (0x1001c + pCodec->pCoreBaseAddr)      #define MCCADDR   (0x10020 + pCodec->pCoreBaseAddr)          #define CPSTS     (0x10028 + pCodec->pCoreBaseAddr)      #define MCUTIR    (0x1002c + pCodec->pCoreBaseAddr)      #define PYDCR	    (0x10030 + pCodec->pCoreBaseAddr)      #define PUVDCR	(0x10034 + pCodec->pCoreBaseAddr)      #define QAR		(0x10038 + pCodec->pCoreBaseAddr)      #define CKR       (0x1003c + pCodec->pCoreBaseAddr)      #define VADR      (0x10044 + pCodec->pCoreBaseAddr)      #define BADR      (0x1004c + pCodec->pCoreBaseAddr)      #define BALR      (0x10050 + pCodec->pCoreBaseAddr)      #define MCIADDR   (0x10058 + pCodec->pCoreBaseAddr)      #define VLDCTL    (0x1005c + pCodec->pCoreBaseAddr)      #define VOP0      (0x10060 + pCodec->pCoreBaseAddr)      #define SCODE     (0x10068 + pCodec->pCoreBaseAddr)      #define VLASTWORD (0x1006c + pCodec->pCoreBaseAddr)      #define VLDSTS    (0x10074 + pCodec->pCoreBaseAddr)	  #define ABADR     (0x10078 + pCodec->pCoreBaseAddr)      #define READ_MCCTL(v)     v=*(volatile unsigned long*)MCCTL;      #define READ_QAR(v)    	v=*(volatile unsigned long*)QAR;      #define READ_VADR(v)		v=*(volatile unsigned long*)VADR;      #define READ_BADR(v)		v=*(volatile unsigned long*)BADR;      #define READ_VOP0(v)  	v=*(volatile unsigned long*)VOP0;      #define READ_CPSTS(v)		v=*(volatile unsigned long*)CPSTS;      #define READ_BALR(v)		v=*(volatile unsigned long*)BALR;      #define READ_VLDCTL(v)    v=*(volatile unsigned long*)VLDCTL;      #define READ_VLASTWORD(v)	v=*(volatile unsigned long*)VLASTWORD;      #define READ_VLDSTS(v)	v=*(volatile unsigned long*)VLDSTS;	//ABF clean      #define READ_ABADR(v)		v=*(volatile unsigned long*)ABADR;