/*++
Module name:

        FRMWRK.c

Abstract:

        This is the FRMWRK Infrastructure module.

Author:

        Michael Anburaj
        URL              : http:\\embedded.n3.net      Email : embeddedeng@hotmail.com

Environment:

        Processor        : EP73XX (32 bit ARM720T RISC core from CIRRUS)
        IDE              : SDT 2.51 & ADS 1.0

--*/

/* ********************************************************************* */

#include "includes.h"
#include "FRMWRK.h"
#include "CONSOL.h"


/* ********************************************************************* */
/* Global definitions */


/* ********************************************************************* */
/* File local definitions */


/* ********************************************************************* */
/* Local functions */

static void __HaltUndef(void)
{
        CONSOL_Printf("Undefined instruction exception!!!\n");
        while(1);
}

static void __HaltSwi(void)
{
        CONSOL_Printf("SWI exception!!!\n");
        while(1);
}

static void __HaltPabort(void)
{
        CONSOL_Printf("Pabort exception!!!\n");
        while(1);
}

static void __HaltDabort(void)
{
        CONSOL_Printf("Dabort exception!!!\n");
        while(1);
}

static void __HaltFiq(void)
{
        CONSOL_Printf("FIQ exception!!!\n");
        while(1);
}

static void __vInitISR(void)
{
        pISR_UNDEF = (unsigned)__HaltUndef;
        pISR_SWI   = (unsigned)__HaltSwi;
        pISR_PABORT= (unsigned)__HaltPabort;
        pISR_DABORT= (unsigned)__HaltDabort;
        pISR_FIQ= (unsigned)__HaltFiq;
}

void __vLogo(void)
{
        CONSOL_Printf("\n\nUCOS_FRAMEWORK Ver %s for EP73XX from CIRRUS %s\n",
                      __mVer,__mDate);
        CONSOL_Printf("COM:115.2kbps,8Bit,NP,CONSOL0 <n+6>(4)+(n)+CS(2)\n");
        CONSOL_Printf("ROM_DADDR:%xh RAM_DADDR:%xh SFR_BADDR: %xh ISR_BADDR:%xh\n",
                    FSADDR,RSADDR, SBADDR,IBADDR);
        CONSOL_Printf("Developed by Michael Anburaj, http:\\embedded.n3.net\n\n");
}


/* ********************************************************************* */
/* Global functions */

void C_IRQHandler(void)
{
        U32 wTemp;

        wTemp = rINTSR1&rINTMR1;

        if(wTemp & BIT_TC1OI)
        {
                OSTimeTick();
                rTC1EOI = 0;               //clear the EOI
        }
        /* Add code for the other IRQ interrupts here */
        else
        {
                CONSOL_Printf("###Error: Illegal Interrupt.\n");
        }
}

/* wTicksPerSec = 10...10000 ticks per sec */
void FRMWRK_vStartTicker(U32 wTicksPerSec)
{
#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
    OS_CPU_SR  cpu_sr;
#endif

        OS_ENTER_CRITICAL ();

//first, set up the timer1 for 512Khz input with prescale mode enabled
        BIT_SET(rSYSCON1,BIT_TC1M);        //set bit 4
        BIT_SET(rSYSCON1,BIT_TC1S);        //set bit 5

        rTC1D = (512000/wTicksPerSec-1);

        //enable timer interrupt by enabling the bit in the interrupt mask register
        rTC1EOI = 0;                       //clear the EOI
        BIT_SET(rINTMR1,BIT_TC1OI);        //set bit 8

        OS_EXIT_CRITICAL ();
 }

void C_vMain(void)
{
        pISR_IRQ = (U32)UCOS_IRQHandler;

        __vInitISR();

        CONSOL_Select(1);
        CONSOL_Init(__nConsolBaud,__nConsolFifoEn);

        __vLogo();

        APP_vMain();
}


/* ********************************************************************* */