/* ads860.h - Motorola MPC860ADS board header *//* Copyright 1984-1997 Wind River Systems, Inc. *//*modification history--------------------01l,06feb99,cn   added support for SDRAM (SPR# 24337), also changed		 N_SIO_CHANNELS to 2 (SPR# 10005).01i,06jan99,cn   added support for FADS860T boards.01h,18feb98,gls  added support for PPC823FADS01g,12nov97,map  added SYS_CPU_FREQ [SPR# 9366]01f,11nov97,hdn  added PC_xxx macros for TFFS.01e,10nov96,tpr  replaved SYS_CLK_FREQ by SPLL_FREQ_REQUESTED.01d,08nov96,tpr  added DEC_CLOCK_FREQ.01c,06nov96,tpr  added macros + clean up.01b,28may96,dzb  changed to 24Mhz clock speed.01a,19apr96,tpr  written.*//*This file contains I/O addresses and related constants for theMotorola MPC860ads board. */#ifndef	INCads860h#define	INCads860h#include "drv/mem/memDev.h"#include "drv/intrCtl/ppc860Intr.h"#define BUS	0				/* bus-less board */#define CPU	PPC860				/* CPU type */#define N_SIO_CHANNELS      2           /* No. serial I/O channels */#define FREQ_20_MHZ		20000000	/* 20 Mhz */#define FREQ_25_MHZ		25000000	/* 25 Mhz */#define FREQ_50_MHZ		50000000	/* 50 Mhz */#define	PC_BASE_ADRS_0		0x02000000	/* PCMCIA base address */#define	PC_SIZE_0		0x00100000	/* PCMCIA mapping size */#define	PC_BASE_ADRS_1		0x04000000	/* PCMCIA base address */#define	PC_SIZE_1		0x02000000	/* PCMCIA mapping size *//*  * SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register. * PLPRCR is set by sysHwInit() in sysLib.c.  * SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h */#define SPLL_MUL_FACTOR	((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)/*  * SPLL Multiplication Factor to get a 20 MHZ running frequency */#define SPLL_MUL_FACTOR_20MHZ	((FREQ_20_MHZ / CRISTAL_FREQ) - 1)#define SPLL_MUL_FACTOR_50MHZ   ((FREQ_50_MHZ / CRISTAL_FREQ) - 1)/* * SPLL Frequency - gives the SPLL real frequency divide by 2 */#define SPLL_FREQ	((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)/* * Baud Rate Generator Clock - gives the Baud Rate Generator Clock (BRGCLK) * Frequency.  */#define BRGCLK_FREQ         FREQ_50_MHZ/*  * Refresh value - defines the number of BRGCLK period between two  * DRAM refresh cycle. */#define REFRESH_VALUE       (BRGCLK_FREQ / (DRAM_REFRESH_FREQ))/*  * Periodic Timer A period - value used to set the PTA bits of * the Machine A Mode Register (MAMR). This register is used to * controle the User_Programmable Machine A (UPM). The UPM is part of * the memory controller. */#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \			  (REFRESH_VALUE /  2))))))/*  * Periodic Timer Prescaler Division Factor - gives the division factor * of the Periodic Timer Prescaler (PTP). The PTP is part of the  * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the * Periodic Timer.  * This macro is used to set the DRAM refresh cycle period. */#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)/* * PTP Value - translate the Periodic Timer Prescaler Division Factor  * to the value to place in the PTP register. */#define PTP_VALUE    (PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \			  MPTPR_PTP_DIV64)))))/* */#define TMBCLK_FREQ	   		CRISTAL_FREQ/* define the decrementer input clock frequency */#define DEC_CLOCK_FREQ		TMBCLK_FREQ/* define system clock rate */#define	SYS_CPU_FREQ		SPLL_FREQ/* Internal Memory Map base Address */#define INTERNAL_MEM_MAP_ADDR   0xFFF00000      /* Base of IMMR */#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes *//* size of the on-board SDRAM */#define SDRAM_SIZE              0x02000000      /* 32 Meg */#define SDRAM_REFRESH_FREQ		64000		/* 64 Khz */ /* CPU type in the PVR */#define CPU_TYPE_860			0x0050		/* value for PPC860 */#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num *//* Ethernet parameters */#ifdef  INCLUDE_CPM				/* CPM ethernet driver */#define INCLUDE_IF_USR#define IF_USR_NAME     "cpm"                   /* device name */#define IF_USR_ATTACH   sysCpmAttach            /* driver attach routine */						/* address of SCC param RAM */#define IF_USR_ARG1     (char *) INTERNAL_MEM_MAP_ADDR + 0x3c00 						/* address of SCC regs */#define IF_USR_ARG2     (int)INTERNAL_MEM_MAP_ADDR + 0x0a00    #define IF_USR_ARG3     (int) IV_SCC1           /* int number for SCC1 */						/* address of transmit BDs */#define IF_USR_ARG4     (int)   INTERNAL_MEM_MAP_ADDR + 0x2800  /* address of receive BDs */						/* address of receive BDs */#define IF_USR_ARG5     (int)   INTERNAL_MEM_MAP_ADDR + 0x2a00#define IF_USR_ARG6     (int) 0x20              /* number of transmit BDs */#define IF_USR_ARG7     (int)   0x40              /* number of receive BDs */#define IF_USR_ARG8     (int) NONE              /* allocate mem for buffers */#endif  /* INCLUDE_CPM */#define DELTA(a,b)        ( abs((int)a - (int)b) )#endif /* INCads860h */