#define 	AT91C_SDRAMC_TRCD_0                    (0x0 << 20) // (SDRAMC) Value :  0#define 	AT91C_SDRAMC_TRCD_1                    (0x1 << 20) // (SDRAMC) Value :  1#define 	AT91C_SDRAMC_TRCD_2                    (0x2 << 20) // (SDRAMC) Value :  2#define 	AT91C_SDRAMC_TRCD_3                    (0x3 << 20) // (SDRAMC) Value :  3#define 	AT91C_SDRAMC_TRCD_4                    (0x4 << 20) // (SDRAMC) Value :  4#define 	AT91C_SDRAMC_TRCD_5                    (0x5 << 20) // (SDRAMC) Value :  5#define 	AT91C_SDRAMC_TRCD_6                    (0x6 << 20) // (SDRAMC) Value :  6#define 	AT91C_SDRAMC_TRCD_7                    (0x7 << 20) // (SDRAMC) Value :  7#define 	AT91C_SDRAMC_TRCD_8                    (0x8 << 20) // (SDRAMC) Value :  8#define 	AT91C_SDRAMC_TRCD_9                    (0x9 << 20) // (SDRAMC) Value :  9#define 	AT91C_SDRAMC_TRCD_10                   (0xA << 20) // (SDRAMC) Value : 10#define 	AT91C_SDRAMC_TRCD_11                   (0xB << 20) // (SDRAMC) Value : 11#define 	AT91C_SDRAMC_TRCD_12                   (0xC << 20) // (SDRAMC) Value : 12#define 	AT91C_SDRAMC_TRCD_13                   (0xD << 20) // (SDRAMC) Value : 13#define 	AT91C_SDRAMC_TRCD_14                   (0xE << 20) // (SDRAMC) Value : 14#define 	AT91C_SDRAMC_TRCD_15                   (0xF << 20) // (SDRAMC) Value : 15#define AT91C_SDRAMC_TRAS         (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles#define 	AT91C_SDRAMC_TRAS_0                    (0x0 << 24) // (SDRAMC) Value :  0#define 	AT91C_SDRAMC_TRAS_1                    (0x1 << 24) // (SDRAMC) Value :  1#define 	AT91C_SDRAMC_TRAS_2                    (0x2 << 24) // (SDRAMC) Value :  2#define 	AT91C_SDRAMC_TRAS_3                    (0x3 << 24) // (SDRAMC) Value :  3#define 	AT91C_SDRAMC_TRAS_4                    (0x4 << 24) // (SDRAMC) Value :  4#define 	AT91C_SDRAMC_TRAS_5                    (0x5 << 24) // (SDRAMC) Value :  5#define 	AT91C_SDRAMC_TRAS_6                    (0x6 << 24) // (SDRAMC) Value :  6#define 	AT91C_SDRAMC_TRAS_7                    (0x7 << 24) // (SDRAMC) Value :  7#define 	AT91C_SDRAMC_TRAS_8                    (0x8 << 24) // (SDRAMC) Value :  8#define 	AT91C_SDRAMC_TRAS_9                    (0x9 << 24) // (SDRAMC) Value :  9#define 	AT91C_SDRAMC_TRAS_10                   (0xA << 24) // (SDRAMC) Value : 10#define 	AT91C_SDRAMC_TRAS_11                   (0xB << 24) // (SDRAMC) Value : 11#define 	AT91C_SDRAMC_TRAS_12                   (0xC << 24) // (SDRAMC) Value : 12#define 	AT91C_SDRAMC_TRAS_13                   (0xD << 24) // (SDRAMC) Value : 13#define 	AT91C_SDRAMC_TRAS_14                   (0xE << 24) // (SDRAMC) Value : 14#define 	AT91C_SDRAMC_TRAS_15                   (0xF << 24) // (SDRAMC) Value : 15#define AT91C_SDRAMC_TXSR         (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles#define 	AT91C_SDRAMC_TXSR_0                    (0x0 << 28) // (SDRAMC) Value :  0#define 	AT91C_SDRAMC_TXSR_1                    (0x1 << 28) // (SDRAMC) Value :  1#define 	AT91C_SDRAMC_TXSR_2                    (0x2 << 28) // (SDRAMC) Value :  2#define 	AT91C_SDRAMC_TXSR_3                    (0x3 << 28) // (SDRAMC) Value :  3#define 	AT91C_SDRAMC_TXSR_4                    (0x4 << 28) // (SDRAMC) Value :  4#define 	AT91C_SDRAMC_TXSR_5                    (0x5 << 28) // (SDRAMC) Value :  5#define 	AT91C_SDRAMC_TXSR_6                    (0x6 << 28) // (SDRAMC) Value :  6#define 	AT91C_SDRAMC_TXSR_7                    (0x7 << 28) // (SDRAMC) Value :  7#define 	AT91C_SDRAMC_TXSR_8                    (0x8 << 28) // (SDRAMC) Value :  8#define 	AT91C_SDRAMC_TXSR_9                    (0x9 << 28) // (SDRAMC) Value :  9#define 	AT91C_SDRAMC_TXSR_10                   (0xA << 28) // (SDRAMC) Value : 10#define 	AT91C_SDRAMC_TXSR_11                   (0xB << 28) // (SDRAMC) Value : 11#define 	AT91C_SDRAMC_TXSR_12                   (0xC << 28) // (SDRAMC) Value : 12#define 	AT91C_SDRAMC_TXSR_13                   (0xD << 28) // (SDRAMC) Value : 13#define 	AT91C_SDRAMC_TXSR_14                   (0xE << 28) // (SDRAMC) Value : 14#define 	AT91C_SDRAMC_TXSR_15                   (0xF << 28) // (SDRAMC) Value : 15// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------#define AT91C_SDRAMC_DA           (0x1 <<  0) // (SDRAMC) Decode Cycle Enable Bit#define 	AT91C_SDRAMC_DA_DISABLE              (0x0) // (SDRAMC) Disable Decode Cycle#define 	AT91C_SDRAMC_DA_ENABLE               (0x1) // (SDRAMC) Enable Decode Cycle// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------#define AT91C_SDRAMC_LPCB         (0x3 <<  0) // (SDRAMC) Low-power Configurations#define 	AT91C_SDRAMC_LPCB_DISABLE              (0x0) // (SDRAMC) Disable Low Power Features#define 	AT91C_SDRAMC_LPCB_SELF_REFRESH         (0x1) // (SDRAMC) Enable SELF_REFRESH#define 	AT91C_SDRAMC_LPCB_POWER_DOWN           (0x2) // (SDRAMC) Enable POWER_DOWN#define 	AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN#define AT91C_SDRAMC_PASR         (0x7 <<  4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)#define AT91C_SDRAMC_TCSR         (0x3 <<  8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)#define AT91C_SDRAMC_DS           (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)#define AT91C_SDRAMC_TIMEOUT      (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled#define 	AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately#define 	AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer#define 	AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------#define AT91C_SDRAMC_RES          (0x1 <<  0) // (SDRAMC) Refresh Error Status// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------#define AT91C_SDRAMC_MD           (0x3 <<  0) // (SDRAMC) Memory Device Type#define 	AT91C_SDRAMC_MD_SDRAM                (0x0) // (SDRAMC) SDRAM Mode#define 	AT91C_SDRAMC_MD_LOW_POWER_SDRAM      (0x1) // (SDRAMC) SDRAM Low Power Mode// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface// *****************************************************************************// *** Register offset in AT91S_SMC structure ***#define SMC_SETUP0      ( 0) //  Setup Register for CS 0#define SMC_PULSE0      ( 4) //  Pulse Register for CS 0#define SMC_CYCLE0      ( 8) //  Cycle Register for CS 0#define SMC_CTRL0       (12) //  Control Register for CS 0#define SMC_SETUP1      (16) //  Setup Register for CS 1#define SMC_PULSE1      (20) //  Pulse Register for CS 1#define SMC_CYCLE1      (24) //  Cycle Register for CS 1#define SMC_CTRL1       (28) //  Control Register for CS 1#define SMC_SETUP2      (32) //  Setup Register for CS 2#define SMC_PULSE2      (36) //  Pulse Register for CS 2#define SMC_CYCLE2      (40) //  Cycle Register for CS 2#define SMC_CTRL2       (44) //  Control Register for CS 2#define SMC_SETUP3      (48) //  Setup Register for CS 3#define SMC_PULSE3      (52) //  Pulse Register for CS 3#define SMC_CYCLE3      (56) //  Cycle Register for CS 3#define SMC_CTRL3       (60) //  Control Register for CS 3#define SMC_SETUP4      (64) //  Setup Register for CS 4#define SMC_PULSE4      (68) //  Pulse Register for CS 4#define SMC_CYCLE4      (72) //  Cycle Register for CS 4#define SMC_CTRL4       (76) //  Control Register for CS 4#define SMC_SETUP5      (80) //  Setup Register for CS 5#define SMC_PULSE5      (84) //  Pulse Register for CS 5#define SMC_CYCLE5      (88) //  Cycle Register for CS 5#define SMC_CTRL5       (92) //  Control Register for CS 5#define SMC_SETUP6      (96) //  Setup Register for CS 6#define SMC_PULSE6      (100) //  Pulse Register for CS 6#define SMC_CYCLE6      (104) //  Cycle Register for CS 6#define SMC_CTRL6       (108) //  Control Register for CS 6#define SMC_SETUP7      (112) //  Setup Register for CS 7#define SMC_PULSE7      (116) //  Pulse Register for CS 7#define SMC_CYCLE7      (120) //  Cycle Register for CS 7#define SMC_CTRL7       (124) //  Control Register for CS 7// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------#define AT91C_SMC_NWESETUP        (0x3F <<  0) // (SMC) NWE Setup Length#define AT91C_SMC_NCSSETUPWR      (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access#define AT91C_SMC_NRDSETUP        (0x3F << 16) // (SMC) NRD Setup Length#define AT91C_SMC_NCSSETUPRD      (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------#define AT91C_SMC_NWEPULSE        (0x7F <<  0) // (SMC) NWE Pulse Length#define AT91C_SMC_NCSPULSEWR      (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access#define AT91C_SMC_NRDPULSE        (0x7F << 16) // (SMC) NRD Pulse Length#define AT91C_SMC_NCSPULSERD      (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------#define AT91C_SMC_NWECYCLE        (0x1FF <<  0) // (SMC) Total Write Cycle Length#define AT91C_SMC_NRDCYCLE        (0x1FF << 16) // (SMC) Total Read Cycle Length// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------#define AT91C_SMC_READMODE        (0x1 <<  0) // (SMC) Read Mode#define AT91C_SMC_WRITEMODE       (0x1 <<  1) // (SMC) Write Mode#define AT91C_SMC_NWAITM          (0x3 <<  5) // (SMC) NWAIT Mode#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  5) // (SMC) External NWAIT disabled.#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  5) // (SMC) External NWAIT enabled in frozen mode.#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  5) // (SMC) External NWAIT enabled in ready mode.#define AT91C_SMC_BAT             (0x1 <<  8) // (SMC) Byte Access Type#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.#define AT91C_SMC_DBW             (0x3 << 12) // (SMC) Data Bus Width#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.#define AT91C_SMC_TDF             (0xF << 16) // (SMC) Data Float Time.#define AT91C_SMC_TDFEN           (0x1 << 20) // (SMC) TDF Enabled.#define AT91C_SMC_PMEN            (0x1 << 24) // (SMC) Page Mode Enabled.#define AT91C_SMC_PS              (0x3 << 28) // (SMC) Page Size#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------