#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is four times faster than the master clock// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask#define AT91C_PMC_LOCKA           (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask#define AT91C_PMC_LOCKB           (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Reset Controller Interface// *****************************************************************************// *** Register offset in AT91S_RSTC structure ***#define RSTC_RCR        ( 0) // Reset Control Register#define RSTC_RSR        ( 4) // Reset Status Register#define RSTC_RMR        ( 8) // Reset Mode Register// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset#define AT91C_RSTC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface// *****************************************************************************// *** Register offset in AT91S_SHDWC structure ***#define SHDWC_SHCR      ( 0) // Shut Down Control Register#define SHDWC_SHMR      ( 4) // Shut Down Mode Register#define SHDWC_SHSR      ( 8) // Shut Down Status Register// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------#define AT91C_SHDWC_SHDW          (0x1 <<  0) // (SHDWC) Processor Reset#define AT91C_SHDWC_KEY           (0xFF << 24) // (SHDWC) Shut down KEY Password// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------#define AT91C_SHDWC_WKMODE0       (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.#define AT91C_SHDWC_CPTWK0        (0xF <<  4) // (SHDWC) Counter On Wake Up 0#define AT91C_SHDWC_WKMODE1       (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.#define AT91C_SHDWC_CPTWK1        (0xF << 12) // (SHDWC) Counter On Wake Up 1#define AT91C_SHDWC_RTTWKEN       (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable#define AT91C_SHDWC_RTCWKEN       (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------#define AT91C_SHDWC_WAKEUP0       (0x1 <<  0) // (SHDWC) Wake Up 0 Status#define AT91C_SHDWC_WAKEUP1       (0x1 <<  1) // (SHDWC) Wake Up 1 Status#define AT91C_SHDWC_FWKUP         (0x1 <<  2) // (SHDWC) Force Wake Up Status#define AT91C_SHDWC_RTTWK         (0x1 << 16) // (SHDWC) Real Time Timer wake Up#define AT91C_SHDWC_RTCWK         (0x1 << 17) // (SHDWC) Real Time Clock wake Up// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface// *****************************************************************************// *** Register offset in AT91S_RTTC structure ***#define RTTC_RTMR       ( 0) // Real-time Mode Register#define RTTC_RTAR       ( 4) // Real-time Alarm Register#define RTTC_RTVR       ( 8) // Real-time Value Register#define RTTC_RTSR       (12) // Real-time Status Register// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface// *****************************************************************************// *** Register offset in AT91S_PITC structure ***#define PITC_PIMR       ( 0) // Period Interval Mode Register#define PITC_PISR       ( 4) // Period Interval Status Register#define PITC_PIVR       ( 8) // Period Interval Value Register#define PITC_PIIR       (12) // Period Interval Image Register// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface// *****************************************************************************// *** Register offset in AT91S_WDTC structure ***#define WDTC_WDCR       ( 0) // Watchdog Control Register#define WDTC_WDMR       ( 4) // Watchdog Mode Register#define WDTC_WDSR       ( 8) // Watchdog Status Register// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface// *****************************************************************************// *** Register offset in AT91S_TC structure ***#define TC_CCR          ( 0) // Channel Control Register#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)#define TC_CV           (16) // Counter Value#define TC_RA           (20) // Register A#define TC_RB           (24) // Register B#define TC_RC           (28) // Register C#define TC_SR           (32) // Status Register#define TC_IER          (36) // Interrupt Enable Register#define TC_IDR          (40) // Interrupt Disable Register#define TC_IMR          (44) // Interrupt Mask Register// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK#define 	AT91C_TC_CLKS_XC0                  (0x5) //