///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_infrastructure_iobs_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The DDR memory clocks are generated here using the differential
//              buffers and the ODDR elemnts in the IOBs.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_infrastructure_iobs_0
  (
   input      CLK,
   output  [`clk_width-1:0]   DDR_CK,
   output  [`clk_width-1:0]   DDR_CK_N
   );

   wire [`clk_width-1:0]      DDR_CK_q;
   wire [`clk_width-1:0]      DDR_CK_N_q;
   wire                       vcc;
   wire                       gnd;

   assign vcc         = 1'b1;
   assign gnd         = 1'b0;

   
  defparam oddr_clk0.SRTYPE = "SYNC";
  defparam oddr_clk0.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk0 
    (
                .Q(DDR_CK_q[0]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
    );

  defparam oddr_clk0_n.SRTYPE = "SYNC";
  defparam oddr_clk0_n.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk0_n 
    (
                 .Q(DDR_CK_N_q[0]),
                 .C(CLK),
                 .CE(vcc),
                 .D1(vcc),
                 .D2(gnd),
                 .R(gnd),
                 .S(gnd)
     );



  defparam oddr_clk1.SRTYPE = "SYNC";
  defparam oddr_clk1.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk1 
    (
                .Q(DDR_CK_q[1]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
    );

  defparam oddr_clk1_n.SRTYPE = "SYNC";
  defparam oddr_clk1_n.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk1_n 
    (
                 .Q(DDR_CK_N_q[1]),
                 .C(CLK),
                 .CE(vcc),
                 .D1(vcc),
                 .D2(gnd),
                 .R(gnd),
                 .S(gnd)
     );



  defparam oddr_clk2.SRTYPE = "SYNC";
  defparam oddr_clk2.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk2 
    (
                .Q(DDR_CK_q[2]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
    );

  defparam oddr_clk2_n.SRTYPE = "SYNC";
  defparam oddr_clk2_n.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk2_n 
    (
                 .Q(DDR_CK_N_q[2]),
                 .C(CLK),
                 .CE(vcc),
                 .D1(vcc),
                 .D2(gnd),
                 .R(gnd),
                 .S(gnd)
     );



  defparam oddr_clk3.SRTYPE = "SYNC";
  defparam oddr_clk3.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk3 
    (
                .Q(DDR_CK_q[3]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
    );

  defparam oddr_clk3_n.SRTYPE = "SYNC";
  defparam oddr_clk3_n.DDR_CLK_EDGE = "OPPOSITE_EDGE";

  ODDR oddr_clk3_n 
    (
                 .Q(DDR_CK_N_q[3]),
                 .C(CLK),
                 .CE(vcc),
                 .D1(vcc),
                 .D2(gnd),
                 .R(gnd),
                 .S(gnd)
     );



   OBUFDS OBUFDS0
        (
         .I(DDR_CK_q[0]),
         .O(DDR_CK[0]),
         .OB(DDR_CK_N[0])
         );


OBUFDS OBUFDS1
        (
         .I(DDR_CK_q[1]),
         .O(DDR_CK[1]),
         .OB(DDR_CK_N[1])
         );


OBUFDS OBUFDS2
        (
         .I(DDR_CK_q[2]),
         .O(DDR_CK[2]),
         .OB(DDR_CK_N[2])
         );


OBUFDS OBUFDS3
        (
         .I(DDR_CK_q[3]),
         .O(DDR_CK[3]),
         .OB(DDR_CK_N[3])
         );



endmodule