#define GPIO_DATA_DIRECTION_HIGH_51_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_50                     18:18
#define GPIO_DATA_DIRECTION_HIGH_50_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_50_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_49                     17:17
#define GPIO_DATA_DIRECTION_HIGH_49_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_49_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_48                     16:16
#define GPIO_DATA_DIRECTION_HIGH_48_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_48_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_47                     15:15
#define GPIO_DATA_DIRECTION_HIGH_47_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_47_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_46                     14:14
#define GPIO_DATA_DIRECTION_HIGH_46_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_46_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_45                     13:13
#define GPIO_DATA_DIRECTION_HIGH_45_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_45_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_44                     12:12
#define GPIO_DATA_DIRECTION_HIGH_44_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_44_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_43                     11:11
#define GPIO_DATA_DIRECTION_HIGH_43_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_43_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_42                     10:10
#define GPIO_DATA_DIRECTION_HIGH_42_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_42_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_41                     9:9
#define GPIO_DATA_DIRECTION_HIGH_41_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_41_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_40                     8:8
#define GPIO_DATA_DIRECTION_HIGH_40_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_40_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_39                     7:7
#define GPIO_DATA_DIRECTION_HIGH_39_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_39_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_38                     6:6
#define GPIO_DATA_DIRECTION_HIGH_38_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_38_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_37                     5:5
#define GPIO_DATA_DIRECTION_HIGH_37_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_37_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_36                     4:4
#define GPIO_DATA_DIRECTION_HIGH_36_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_36_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_35                     3:3
#define GPIO_DATA_DIRECTION_HIGH_35_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_35_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_34                     2:2
#define GPIO_DATA_DIRECTION_HIGH_34_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_34_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_33                     131
#define GPIO_DATA_DIRECTION_HIGH_33_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_33_OUTPUT              1
#define GPIO_DATA_DIRECTION_HIGH_32                     0:0
#define GPIO_DATA_DIRECTION_HIGH_32_INPUT               0
#define GPIO_DATA_DIRECTION_HIGH_32_OUTPUT              1

#define GPIO_INTERRUPT_SETUP                            0x010010
#define GPIO_INTERRUPT_SETUP_TRIGGER_54                 22:22
#define GPIO_INTERRUPT_SETUP_TRIGGER_54_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_54_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_53                 21:21
#define GPIO_INTERRUPT_SETUP_TRIGGER_53_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_53_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_52                 20:20
#define GPIO_INTERRUPT_SETUP_TRIGGER_52_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_52_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_51                 19:19
#define GPIO_INTERRUPT_SETUP_TRIGGER_51_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_51_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_50                 18:18
#define GPIO_INTERRUPT_SETUP_TRIGGER_50_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_50_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_49                 17:17
#define GPIO_INTERRUPT_SETUP_TRIGGER_49_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_49_LEVEL           1
#define GPIO_INTERRUPT_SETUP_TRIGGER_48                 16:16
#define GPIO_INTERRUPT_SETUP_TRIGGER_48_EDGE            0
#define GPIO_INTERRUPT_SETUP_TRIGGER_48_LEVEL           1
#define GPIO_INTERRUPT_SETUP_ACTIVE_54                  14:14
#define GPIO_INTERRUPT_SETUP_ACTIVE_54_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_54_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_53                  13:13
#define GPIO_INTERRUPT_SETUP_ACTIVE_53_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_53_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_52                  12:12
#define GPIO_INTERRUPT_SETUP_ACTIVE_52_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_52_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_51                  11:11
#define GPIO_INTERRUPT_SETUP_ACTIVE_51_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_51_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_50                  10:10
#define GPIO_INTERRUPT_SETUP_ACTIVE_50_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_50_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_49                  9:9
#define GPIO_INTERRUPT_SETUP_ACTIVE_49_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_49_HIGH             1
#define GPIO_INTERRUPT_SETUP_ACTIVE_48                  8:8
#define GPIO_INTERRUPT_SETUP_ACTIVE_48_LOW              0
#define GPIO_INTERRUPT_SETUP_ACTIVE_48_HIGH             1
#define GPIO_INTERRUPT_SETUP_ENABLE_54                  6:6
#define GPIO_INTERRUPT_SETUP_ENABLE_54_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_54_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_53                  5:5
#define GPIO_INTERRUPT_SETUP_ENABLE_53_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_53_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_52                  4:4
#define GPIO_INTERRUPT_SETUP_ENABLE_52_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_52_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_51                  3:3
#define GPIO_INTERRUPT_SETUP_ENABLE_51_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_51_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_50                  2:2
#define GPIO_INTERRUPT_SETUP_ENABLE_50_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_50_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_49                  1:1
#define GPIO_INTERRUPT_SETUP_ENABLE_49_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_49_INTERRUPT        1
#define GPIO_INTERRUPT_SETUP_ENABLE_48                  0:0
#define GPIO_INTERRUPT_SETUP_ENABLE_48_GPIO             0
#define GPIO_INTERRUPT_SETUP_ENABLE_48_INTERRUPT        1

#define GPIO_INTERRUPT_STATUS                           0x010014
#define GPIO_INTERRUPT_STATUS_54                        22:22
#define GPIO_INTERRUPT_STATUS_54_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_54_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_54_RESET                  1
#define GPIO_INTERRUPT_STATUS_53                        21:21
#define GPIO_INTERRUPT_STATUS_53_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_53_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_53_RESET                  1
#define GPIO_INTERRUPT_STATUS_52                        20:20
#define GPIO_INTERRUPT_STATUS_52_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_52_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_52_RESET                  1
#define GPIO_INTERRUPT_STATUS_51                        19:19
#define GPIO_INTERRUPT_STATUS_51_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_51_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_51_RESET                  1
#define GPIO_INTERRUPT_STATUS_50                        18:18
#define GPIO_INTERRUPT_STATUS_50_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_50_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_50_RESET                  1
#define GPIO_INTERRUPT_STATUS_49                        17:17
#define GPIO_INTERRUPT_STATUS_49_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_49_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_49_RESET                  1
#define GPIO_INTERRUPT_STATUS_48                        16:16
#define GPIO_INTERRUPT_STATUS_48_INACTIVE               0
#define GPIO_INTERRUPT_STATUS_48_ACTIVE                 1
#define GPIO_INTERRUPT_STATUS_48_RESET                  1