?? fw.s
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;******************************************************************************
;*
;* System On Chip(SOC)
;*
;* Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
;* Copyright (c) 2002 Mobile Solution Project Team, Samsung Electronics, Inc.
;* All rights reserved.
;*
;* This software is the confidential and proprietary information of Samsung
;* Electronics, Inc("Confidential Information"). You Shall not disclose such
;* Confidential Information and shall use it only in accordance with the terms
;* of the license agreement you entered into Samsung.
;*
;******************************************************************************
OPT 2
INCLUDE kxarm.h
INCLUDE oalintra.inc
INCLUDE reg2410.a
OPT 1
OPT 128
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
LED_ON $data
LDR r10, =0x56000054
LDR r11, =$data
EOR r11, r11, #0xF
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
VLED_ON $data
LDR r10, =0xB1600054
LDR r11, =$data
EOR r11, r11, #0xF
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
IMPORT KernelStart
IMPORT ARMClearUTLB
IMPORT ARMFlushICache
IMPORT ARMFlushDCache
FCLK EQU (203)
PLLVAL EQU (((0xa1 << 12) + (0x3 << 4) + 0x1))
R1_iA EQU (1 << 31)
R1_nF EQU (1 << 30)
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS EQU 6
DCACHE_LINES_PER_SET EQU 64
DCACHE_NUM_SETS EQU 8
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU 32
SLEEPDATA_BASE_VIRTUAL EQU 0xAC058000 ; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL EQU 0x30058000
WORD_SIZE EQU (4)
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start )
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE )
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE )
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE )
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE )
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE )
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE )
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE )
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE )
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE )
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE )
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE )
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE )
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE )
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE )
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE )
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE )
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE )
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE )
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE )
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE )
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE )
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE )
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE )
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE )
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE )
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
MMU_CTL_MASK EQU 0x3FFF0000
MMU_TTB_MASK EQU 0x00003FFF
MMU_ID_MASK EQU 0xFFFFFFF0
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80
F_Bit EQU 0x40
BIT_SELFREFRESH EQU (1<<22)
HandleFIQ EQU 0x33ffff1c
;**
; * StartUp - Image EntryPoint
; *
; * @return .
; * @param .
; *
STARTUPTEXT
LEAF_ENTRY StartUp
; Jump over power-off code.
;
1 b ResetHandler
str r1, [r0] ; Enable SDRAM self-refresh
str r3, [r2] ; MISCCR Setting
str r5, [r4] ; Power Off !!
b .
[ {FALSE}
1 b ResetHandler
b %B1 ;handler for Undefined mode
b %B1 ;handler for SWI interrupt
b %B1 ;handler for PAbort
b %B1 ;handler for DAbort
b %B1 ;reserved
b %B1 ;handler for IRQ interrupt
;b HandlerFIQ ;handler for FIQ interrupt
ENTER_POWER_OFF ;FIQ Handler
; LED_ON 0x4
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x20
str r1,[r0]
ldr r5,=REFRESH
ldr r6,[r5]
orr r6, r6, #BIT_SELFREFRESH
ldr r3,=MISCCR
ldr r4,[r3]
orr r4,r4,#(7<<17)
ldr r2,=0x7fff8
ldr r1,=CLKCON
mov r0,#16
b _EPO ;This code isn't needed for code on the ROM
ALIGN 32
_EPO
1 str r6, [r5] ;Enable SDRAM self-refresh
2 subs r0,r0,#1 ;Wait until self-refresh is issued,which may not be needed.
bne %B2
str r4,[r3] ;Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
str r2,[r1] ;CPU will enter into POWER_OFF mode.
b .
]
LTORG
ResetHandler
; LED_ON 0xa
ldr r0, = INTMSK
ldr r1, = ~BIT_BAT_FLT ; all interrupt disable, nBATT_FLT =enabled
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7ff ;all sub interrupt disable
str r1, [r0]
ldr r0, = INTMOD
ldr r1, = BIT_BAT_FLT ; set all interrupt as IRQ, BAT_FLT = FIQ
str r1, [r0]
bl ARMClearUTLB
bl ARMFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl ARMFlushDCache
nop
nop
nop
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; watch dog disable
ldr r1, = 0x0
str r1, [r0]
; ldr r0, = INTMSK
; ldr r1, = 0xffffffff ; all interrupt disable
; str r1, [r0]
; ldr r0, = INTSUBMSK
; ldr r1, = 0x7ff ;all sub interrupt disable
; str r1, [r0]
; ldr r0, = INTMOD
; mov r1, #0x0 ; set all interrupt as IRQ
; str r1, [r0]
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x0 = 1:1:1 , 0x1 = 1:1:2
; 0x2 = 1:2:2 , 0x3 = 1:2:4, 0x8 = 1:4:4
str r1, [r0]
ands r1, r1, #0x2 ; Make AsyncBusMode
beq %F1
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
1
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0xffffff
str r1, [r0]
ldr r0, = MPLLCON ; Configure MPLL
; Fin=12MHz, Fout=50MHz
ldr r1, = PLLVAL
str r1, [r0]
ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
ldr r1, = ((0x48 << 12) + (0x3 << 4) + 0x2)
str r1, [r0]
mov r0, #0x2000
1
subs r0, r0, #1
bne %B1
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2
beq %F2 ; if not wakeup from PowerOffmode
; Skip MISCCR setting
b %F3 ; if wakeup from PowerOff mode
; goto Power-up code.
; Watchdog reset
2
tst r10, #0x4 ; In case of the wake-up from Watchdog reset,
; go to SDRAM start address(0x3020_0000)
beq %F4 ; If not wakeup from Watchdog reset,
; goto Normal Mode.
mov r0, #4
str r0, [r1] ; Clear the GSTATUS2. Because same code is located in memory address.
; Set memory control registers
add r0, pc, #SMRDATA - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
loop0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop0
mov r1, #256
loop1
subs r1, r1, #1 ; wait until the SelfRefresh is released.
bne loop1
ldr r2, =0x201000 ; offset into the RAM
add r2, r2, #0x30000000 ; add physical base
mov pc, r2 ; & jump to StartUp address
b .
; Case of Power-off reset
3
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1] ; I don't know why, Just fallow Sample Code.
bic r0, r0, #(7 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0, [r1]
; - - - - - - - - - - - - - - - - - - - - - - -
; Add for Power Management
; :::::::::::::::::::::::::::::::::::::::::::::
4
add r0, pc, #SMRDATA - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
1
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B1
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
tst r10, #0x2
beq BringUpWinCE ; Normal Mode Booting
; Recover Process : Starting Point
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
mov r2, #0
ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on
40
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b40 ; loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
teq r2, r3 ; compare to what we saved before going to sleep
; bne BringUpWinCE ; bad news - do a cold boot - If emergency power off case, normal booting.
bne JumpToRAM ; bad news - do a cold boot - If emergency power off case, normal booting.
b MMUENABLE
JumpToRAM
ldr r2, =0x201000 ; offset into the RAM
ldr r3, =0x30000000 ; add physical base
add r2, r2, r3
mov pc, r2 ; & jump to StartUp address
MMUENABLE
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address
nop
nop
nop
nop
nop
; if software reset
;mov r1, #0
mov r1, #0x38000000
teq r1, r7
bne %f1
bl BringUpWinCE
; wakeup routine
1
mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s(Awake_address)
mov pc, r7 ; & jump to new virtual address (back up Power management stack)
nop
; - - - - - - - - - - - - - - - - - - - - - - -
; Add for Power Management
; :::::::::::::::::::::::::::::::::::::::::::::
BringUpWinCE
ldr r0, = GPFDAT
mov r1, #0x60
str r1, [r0]
add r0, pc, #OEMAddressTable - (. + 8)
bl KernelStart
LTORG
SMRDATA DATA
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD 0x1f74;//((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
DCD 0xB2 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7
INCLUDE map.a
TEXTAREA
;**
; * CPUPowerWDReset - Software reset routine. Use watchdog timer and SDRAM to self-refresh mode.
; *
; * Entry none
; * Exit none
; * Uses r0-r3
; *
LEAF_ENTRY CPUPowerWDReset
; VLED_ON 0xb
;Watchdog reset enable.
ldr r1, =vWTCON
ldr r0, [r1]
orr r0, r0, #(1<<5) ; Enable watchdog timer.
str r0, [r1]
ldr r0, =vREFRESH
ldr r1, [r0] ; r1=rREFRESH
orr r1, r1, #(1 << 22)
;Set memory control self-refersh
ldr r0,=vREFRESH
ldr r3,[r0] ;r3=rREFRESH, may fill TLB
orr r3, r3, #BIT_SELFREFRESH
b %F1
ALIGN 32 ;The following instructions will be in I-Cache
1
str r3, [r0] ;Enable SDRAM self-refresh
b .
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