PINSEL0     EQU 0xE002C000
PINSEL2     EQU 0xE002C014

BCFG0       EQU 0xFFE00000
BCFG1       EQU 0xFFE00004
BCFG2       EQU 0xFFE00008
BCFG3       EQU 0xFFE0000C


MASK_MODE		EQU		0x0000003F
MODE_SVC32		EQU		0x00000013

I_BIT           EQU     0x80 ; when I bit is set, IRQ is disabled
F_BIT           EQU     0x40 ; when F bit is set, FIQ is disabled


;引入的外部標號在這聲明
    IMPORT  main                            ;C語言主程序入口 
	IMPORT  TargetResetInit                 ;目標板基本初始化
	
    CODE32
    PRESERVE8
    AREA    vectors,CODE,READONLY
        ENTRY
;中斷向量表
Reset
        LDR     PC, ResetAddr
        LDR     PC, UndefinedAddr
        LDR     PC, SWI_Addr
        LDR     PC, PrefetchAddr
        LDR     PC, DataAbortAddr
        DCD     0xb9205f80
        LDR     PC, IRQ_Addr
        LDR     PC, FIQ_Addr

ResetAddr			DCD		ResetInit
UndefinedAddr       DCD     0x81000004
SWI_Addr            DCD     0x81000008
PrefetchAddr        DCD     0x8100000c
DataAbortAddr       DCD     0x81000010
Nouse               DCD     0
IRQ_Addr            DCD     0x81000018
FIQ_Addr            DCD     0x8100001c

;********************************************************************************************************/
ResetInit

;disable interrupts in CPU and switch to SVC32 mode

	MRS	r0, cpsr
	BIC	r0, r0, #MASK_MODE
	ORR	r0, r0, #MODE_SVC32
	ORR r0, r0, #I_BIT
	ORR r0, r0, #F_BIT
	MSR	cpsr_c, r0
	
;Initial extenal bus controller.
;初始化外部總線控制器，根據目標板決定配置

        LDR     R0, =PINSEL2
    IF :DEF: EN_CRP
        LDR     R1, =0x0f814910
    ELSE
        LDR     R1, =0x0f814914
    ENDIF
        STR     R1, [R0]

        LDR     R0, =BCFG0
        LDR     R1, =0x10001460
        STR     R1, [R0]

        LDR     R0, =BCFG1
        LDR     R1, =0x10001460
        STR     R1, [R0]

;        LDR     R0, =BCFG2
;        LDR     R1, =0x2000ffef
;        STR     R1, [R0]

;        LDR     R0, =BCFG3
        LDR     R1, =0x10001460
;        STR     R1, [R0]
        
        LDR		SP, =0x40003000
        
        BL      TargetResetInit         ;目標板基本初始化
                                        
        BL      main 					;跳轉到c語言入口
        

        LDR     R0, =BCFG0				;bank0: 32bit, external flash
        LDR     R1, =0x20007c67			;set to high speed for loading kernel
        STR     R1, [R0]

        LDR     R0, =BCFG1				;bank1: 32bit, external pSRAM
        LDR     R1, =0x20007c67			;set to low speed for stability
        STR     R1, [R0]

        LDR     R0, =0                  ;chenkang add set R0 to zero
        LDR		PC, =0x81008000			;jump to uClinux start up

        END


;/*********************************************************************************************************
;**                            End Of File
;********************************************************************************************************/