module	adc(adda,ale,start,eoc,oe,clk,rst_,data_in,data_out);
	input	eoc,clk,rst_;
	input	[7:0] data_in;
	output	adda,ale,start,oe;
	reg		adda,ale,start,oe;
	output	[7:0] data_out;
	reg		[7:0] data_out;
	reg 	[2:0]	state;
	parameter	IDLE=3'd0,A=3'd1,B=3'd2,C=3'd3,D=3'd4;
always @ (posedge clk or negedge rst_)
	if(!rst_)
		begin
		adda<=1;
		ale<=0;
		start<=0;
		oe<=0;
		data_out<=0;
		end
	else
	case(state)
	 	IDLE:	begin
			adda<=1;
			ale<=0;
			start<=0;
			oe<=0;
			state<=A;
			end
		A:	begin
			adda<=1;
			ale<=1;
			start<=0;
			oe<=0;
			state<=B;
			end
		B:	begin
			adda<=1;
			ale<=0;
			start<=1;
			oe<=0;
			state<=C;
			end
		C:	begin
			adda<=1;
			ale<=0;
			start<=0;
			if(!eoc)	
				begin
				oe<=1;
				state<=D;
				end
			else		
				begin
				oe<=0;
				state<=C;
				end
			end
		D:	begin
			adda<=1;
			ale<=0;
			start<=0;
			oe<=1;
			data_out<=data_in;
			state<=IDLE;
			end
		default:;
	endcase
endmodule