/*******************************************************************************
*
*  File name:              zl5011xAddrMap.h
*
*  Version:                40
*
*  Author:                 MRC
*
*  Date created:           08/02/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*
*     Contains the offset addresses for the blocks and any device specific
*     constants - number of streams etc.
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     08/02/2002  MRC      Creation
*  2     15/02/2002  MRC      Update
*  3     28/02/2002  MRC      Update
*  4     19/03/2002  MRC      Update
*  5     27/03/2002  MRC      Added PAC block
*  6     27/03/2002  LCW      Added ADM block
*  7     03/04/2002  MRC      Added PAC DCO constants
*  8     03/04/2002  MRC      Moved ADM block
*  9     04/04/2002  MRC      Added internal memory size constant
*  10    09/04/2002  MRC      Defined the correct base addresses for
*                               the blocks
*  11    15/04/2002  WD       Base addresses changed in the device
*  12    16/04/2002  MRC      Added defines for the PTX block
*  13    23/04/2002  MRC      Changed Authur to Author in the header
*  14    07/05/2002  MRC      Added PKC constants.
*  15    13/05/2002  MRC      Added more PKC constants.
*  16    15/05/2002  LCW      Added more PKC constants.
*  17    16/05/2002  MRC      Added channel bit regs for TIF channel enable
*  18    05/06/2002  MRC      Added Packet defines - removed from zl5011x.h
*  19    10/06/2002  MRC      Added RTP constant
*  20    10/06/2002  MRC      Redefined packet header size
*  21    12/06/2002  MRC      Added CPQ default definitions
*  22    13/06/2002  MRC      Removed a couple of PKC definitions
*  23    19/05/2002  MRC      Updated following PTX block change
*  24    20/05/2002  LCW      Added interrupt constant
*  25    21/06/2002  PJE      Added MAC stats size
*  26    24/06/2002  MRC      Changed number of DS3 streams
*  27    18/07/2002  MRC      Added packet memory defines
*  28    06/08/2002  MRC      Added number of pkc pre-processor matches
*  29    20/08/2002  DP       Changed base address for TFQ, PKC, PLA and TFM
*  30    19/09/2002  MRC      Moved some PAC variables into the PAC header
*  31    30/10/2002  MRC      Started variant modifications
*  32    31/10/2002  MRC      Added variants + minor fixes
*  33    10/01/2003  MRC      Removed extra definiton of internal memory size
*  34    30/04/2003  JFE      Changed definition of number of protocol entries
*                             in the PKC in accordance with errata 2.56
*  35    27/05/2003  MRC      Corrected definition for internal memory size
*  36    11/08/2003  MRC      Updated CPQ queues define
*  37    06/09/2004  APL      Updated a comment to allow for device variants
*  38    17/09/2004  MRC      Added default for packet queue granule threshold
*  39    21/01/2005  MRC      Added support for restricted processor address map
*  40    21/07/2005  MRC      Added discard port definitions
*
*******************************************************************************/

#ifndef _ZL5011X_ADDR_MAP_H
#define _ZL5011X_ADDR_MAP_H

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _ZL5011X_RESTRICTED_ADDR_MAP
   /*
      The address map proposed here is for use where there is limited address space
      on the host processor. This relies on the fact that address bits 15 : 2 are
      connected directly to the device and the upper address ranges are remapped using
      external logic. That is CPU address bits 21:16 are mapped to device address bits
      23:16 as follows:-

         000000 - 08FFFF => 000000 08FFFF (800000 88FFFF)   internal memory
         090000 - 0FFFFF => 200000 26FFFF (A00000 A6FFFF)   blocks CPU through PKI
         100000 - 11FFFF => 400000 41FFFF (C00000 C1FFFF)   PKC
         120000 - 19FFFF => 500000 57FFFF (D00000 D7FFFF)   PLA
         1A0000 - 1DFFFF => 600000 63FFFF (E00000 E3FFFF)   TFM
         1E0000 - 1EFFFF => 6F0000 6FFFFF (EF0000 EFFFFF)   TFM interrupt
         1F0000 - 22FFFF => 6F0000 73FFFF (F00000 F3FFFF)   TFQ (contiguous with TFM interrupt)

     This is merely a suggested mapping for the address bits, and it may be that
     an alternative scheme is more practical in order to achieve timing.
   */

   /* the external memory is not available in this mode, but is mapped to 0 for
      compatibility */
   #define ZL5011X_EXT_MEM_BASE    0x00000000
   #define ZL5011X_INT_MEM_BASE    0x00000000

   #define ZL5011X_CPU_BASE        0x00090000
   #define ZL5011X_CPQ_BASE        0x00098000
   #define ZL5011X_ADM_BASE        0x000A0000
   #define ZL5011X_MM_BASE         0x000A8000
   #define ZL5011X_GM_BASE         0x000B0000
   #define ZL5011X_RTP_BASE        0x000B8000
   #define ZL5011X_TIF_BASE        0x000C0000
   #define ZL5011X_PAC_BASE        0x000C8000
   #define ZL5011X_TM_BASE         0x000D8000
   #define ZL5011X_PKQ_BASE        0x000E0000
   #define ZL5011X_PTX_BASE        0x000E8000
   #define ZL5011X_PRX_BASE        0x000F0000
   #define ZL5011X_PKI_BASE        0x000F8000

   #define ZL5011X_PKC_BASE        0x00100000
   #define ZL5011X_PLA_BASE        0x00120000
   #define ZL5011X_TFM_BASE        0x001a0000
   #define ZL5011X_TFQ_BASE        0x001f0000

#else

   /* the bottom of the device's address space is used to access the external
      and internal memories */
   #define ZL5011X_EXT_MEM_BASE    0x00000000
   #define ZL5011X_INT_MEM_BASE    0x00800000

   #define ZL5011X_CPU_BASE        0x00A00000
   #define ZL5011X_CPQ_BASE        0x00A08000
   #define ZL5011X_ADM_BASE        0x00A10000
   #define ZL5011X_MM_BASE         0x00A18000
   #define ZL5011X_GM_BASE         0x00A20000
   #define ZL5011X_RTP_BASE        0x00A28000
   #define ZL5011X_TIF_BASE        0x00A30000
   #define ZL5011X_PAC_BASE        0x00A38000
   #define ZL5011X_TM_BASE         0x00A48000
   #define ZL5011X_PKQ_BASE        0x00A50000
   #define ZL5011X_PTX_BASE        0x00A58000
   #define ZL5011X_PRX_BASE        0x00A60000
   #define ZL5011X_PKI_BASE        0x00A68000

   #define ZL5011X_PKC_BASE        0x00C00000
   #define ZL5011X_PLA_BASE        0x00D00000
   #define ZL5011X_TFM_BASE        0x00E00000
   #define ZL5011X_TFQ_BASE        0x00F00000

#endif

/* device specific parameters */
#define ZL5011X_INT_MEMORY_SIZE_IN_BYTES    0x84000
#define ZL5011X_MEMORY_NUM_HEAP_ALLOCS      255

#define ZL5011X_MAX_NUMBER_CONTEXTS      128
#define ZL5011X_MAX_NUMBER_STREAMS       32
#define ZL5011X_MAX_NUMBER_CHANNELS      1024
#define ZL5011X_MAX_CHANNELS_PER_STREAM  128
#define ZL5011X_NUMBER_STREAM_BIT_REGS   (((ZL5011X_MAX_NUMBER_STREAMS - 1) / 32) + 1)
#define ZL5011X_NUMBER_CHANNEL_BIT_REGS  (((ZL5011X_MAX_NUMBER_CHANNELS - 1) / 32) + 1)

#define ZL5011X_MAX_JITTER_BUFFER_US     200000   /* 200ms is largest buffer */

/* constants to describe the granule size */
#define ZL5011X_GRANULE_DATA_SIZE                 (Uint32T)64
#define ZL5011X_GRANULE_DESCRIPTOR_SIZE           (Uint32T)16

/* Task Manager defines */
#define ZL5011X_TM_NUM_SRC_PORTS                  (Uint32T)4
#define ZL5011X_TM_NUM_DEST_PORTS                 (Uint32T)5

/* Packet TX defines */
#define ZL5011X_PTX_LOW_HEADER_MAX_LEN            (Uint32T)64
#define ZL5011X_RTP_HIGH_HEADER_MAX_LEN           (Uint32T)24

/* the packet Tx uses headers for host to Lan flows. The number of
   headers and the start MPID for them are given below */
#define ZL5011X_PKT_TX_NUM_HOST_HEADERS           (Uint32T)16
#define ZL5011X_PKT_TX_NUM_CONTEXT_HEADERS        ZL5011X_MAX_NUMBER_CONTEXTS

/* PKC defines */
#define ZL5011X_PKC_NUM_FILTER_ENTRIES            (Uint32T)8
#define ZL5011X_PKC_NUM_PROTOCOL_ENTRIES          (Uint32T)4
#define ZL5011X_PKC_NUM_CLASSIFY_ENTRIES          (Uint32T)272

#define ZL5011X_PKC_CLASSIFY_NUM_MATCH_FIELDS     (Uint32T)12
#define ZL5011X_PKC_CLASSIFY_NUM_CHECK_FIELDS     (Uint32T)11

#define ZL5011X_PKC_PROTOCOL_NUM_MATCH_FIELDS     (Uint32T)64

#define ZL5011X_PKC_PROTOCOL_MAX_SEQ_BYTES        (Uint32T)2
#define ZL5011X_PKC_PROTOCOL_MAX_TIMESTAMP_BYTES  (Uint32T)4
#define ZL5011X_PKC_PROTOCOL_MAX_LENGTH_BYTES     (Uint32T)2

/* define for the CPU queue */
#define ZL5011X_CPQ_QUEUES                        1
#define ZL5011X_CPQ_DEFAULT_GRAN_THLD             (Uint32T)100
#define ZL5011X_CPQ_DEFAULT_PACKET_DROP_MODE      ZL5011X_TRUE

/* define for the CPU block*/
#define ZL5011X_CPU_DEFAULT_TIMEOUT               128

/* various defines for the packet interface */
#define ZL5011X_PKQ_DEFAULT_TOTAL_GRAN_THLD       (Uint32T)1000
#define ZL5011X_PKQ_DEFAULT_QUEUE_GRAN_THLD       (Uint32T)200
#define ZL5011X_PKQ_DEFAULT_DISCARD_GRAN_THLD     (Uint32T)1
#define ZL5011X_PKQ_DEFAULT_PACKET_DROP_MODE      ZL5011X_TRUE
#define ZL5011X_PKQ_DEFAULT_PORT                  (Uint32T)0
#define ZL5011X_PKQ_DEFAULT_QUEUE                 (Uint32T)3

#define ZL5011X_PKQ_NUM_QUEUES                    4
#define ZL5011X_MAX_NUM_LAN_PORTS                 4  /* This is the absolute maximum number of LAN ports supported
                                                      by this device family. Particular devices in the
                                                      family may have fewer ports which will be indicated in the
                                                      zl5011xParams->devLimits structure */

/* definition for an unavailable port than can be used to sink
   packets that need to be discarded. Used for discarding packets
   from a dummy context used to stimulate Wan Tx context teardown
   and for redirecting packets in the event of a local LOS, when it
   does not make sense to transmit the packets to the slave. */
#define ZL5011X_PACKET_DISCARD_PORT               ZL5011X_MAX_NUM_LAN_PORTS

/* Size of MAC address in bytes       */
#define ZL5011X_MAC_SIZE                          0x006

/* Size of Mac Stats for one port      (=32 x 32bit registers) */
#define ZL5011X_PKI_MAC_STATS_SIZE          0x20

/* Max length of string fields stored in the  MIB */
#define ZL5011X_STRING_SIZE                       0x100

#define ZL5011X_NUMBER_OF_INTERRUPTS              (Uint32T)3

#ifdef __cplusplus
}
#endif

#endif