/*******************************************************************************
*
*  File name:              zl5011xCpuMap.h
*
*  Version:                21
*
*  Author:                 PJE
*
*  Date created:           21/03/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*
*  This is the register definitions header file for CPU block.
*  It contains the register offsets and bit field definitions.
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     26/03/2002  PJE      unit compiles OK.
*  2     26/03/2002  PJE      update.
*  3     26/03/2002  PJE      runs.
*  4     27/03/2002  PJE      BLOCK_ID not needed
*  5     16/04/2002  MRC      Changed Authur to Author in the header
*  6     15/05/2002  PJE      TIMEOUT handling
*  7     15/05/2002  PJE      TIMEOUT handling
*  8     16/05/2002  PJE      TIMEOUT handling
*  9     16/05/2002  PJE      bug
*  10    11/06/2002  MRC      Added timeout mask bits
*  11    05/08/2002  PJE      timeout & source defines swopped
*  12    12/09/2002  PJE      New zl5011xCpuDmaSetPadding() &
*                             zl5011xCpuDmaSetDreqPolarity debugging.
*  13    23/09/2002  ARW      Added a new macro
*  14    07/10/2002  ARW      Added new bit definition
*  15    08/10/2002  PJE      Added bit defn for  zl5011xCpuDmaGetIntrStatus
*  16    16/10/2002  ARW      Inverted some of the bits for the constat reg
*  17    24/10/2002  ARW      Added extra bits to constat register.
*                             Renamed (for clarity) some bits in constat reg
*                             Added bit definitions for PTH and PRH
*  18    31/10/2002  MRC      Added variants + minor fixes
*  19    21/03/2003  ARW      Reversed DMA in and out addresses
*  20    07/04/2003  ARW      Moved macro to CPQ map file
*  21    19/10/2004  APL      Added CPU Debug States register
*
*******************************************************************************/

#ifndef _ZL5011X_CPU_MAP_H
#define _ZL5011X_CPU_MAP_H

#ifdef __cplusplus
extern "C" {
#endif

/* addresses for the registers */
#define ZL5011X_CPU_CONSTAT           ZL5011X_CPU_BASE + 0x00000   /*  control status reg */
#define ZL5011X_CPU_RESOURCE          ZL5011X_CPU_BASE + 0x00004   /*  Resource reg */
#define ZL5011X_CPU_PACKET_TX         ZL5011X_CPU_BASE + 0x00008   /*  Granule Data In reg */
#define ZL5011X_CPU_PACKET_RX         ZL5011X_CPU_BASE + 0x0000C   /*  Granule Data Out reg */
#define ZL5011X_CPU_RX_SEQ_NO         ZL5011X_CPU_BASE + 0x00010   /*  Rx Sequence Number reg */
#define ZL5011X_CPU_TM_WORD1          ZL5011X_CPU_BASE + 0x00014   /*  DMA Bypass mode
task manager word 1 */
#define ZL5011X_CPU_TM_WORD2          ZL5011X_CPU_BASE + 0x00018   /*  DMA Bypass mode
task manager word 2 */
#define ZL5011X_CPU_TM_WORD3          ZL5011X_CPU_BASE + 0x0001c   /*  DMA Bypass mode
task manager word 3 */
#define ZL5011X_CPU_TM_WORD4          ZL5011X_CPU_BASE + 0x00020   /*  DMA Bypass mode
task manager word 4 */
#define ZL5011X_CPU_TM_SUBMIT         ZL5011X_CPU_BASE + 0x00024   /*  DMA Bypass mode
submit TM message  */
#define ZL5011X_CPU_CPQ_HEAD          ZL5011X_CPU_BASE + 0x00028   /*  DMA Bypass mode
CPQ head pointer */
#define ZL5011X_CPU_CPQ_UPDATE        ZL5011X_CPU_BASE + 0x0002C   /*  DMA Bypass mode
CPQ update data */
#define ZL5011X_CPU_CPQ_SUBMIT        ZL5011X_CPU_BASE + 0x00030   /*  DMA Bypass mode
CPQ update submit */
#define ZL5011X_CPU_GM_GRN_PTR        ZL5011X_CPU_BASE + 0x00034   /*  DMA Bypass mode
GM granule fetch */
#define ZL5011X_CPU_GM_RLS_HEAD       ZL5011X_CPU_BASE + 0x00038   /*  DMA Bypass mode
GM granule release */
#define ZL5011X_CPU_GM_RLS_TAIL       ZL5011X_CPU_BASE + 0x0003C   /*  DMA Bypass mode
GM granule release */
#define ZL5011X_CPU_GM_RLS_SUBMIT     ZL5011X_CPU_BASE + 0x00040   /*  DMA Bypass mode
GM granule release */
#define ZL5011X_CPU_TIMEOUT_PERIOD    ZL5011X_CPU_BASE + 0x00044   /* elapsed no of clock cycles
                                                                     before HCI_TIMEOUT */
#define ZL5011X_CPU_TIMEOUT_SOURCE    ZL5011X_CPU_BASE + 0x00048   /*  address of failing slave*/
#define ZL5011X_CPU_DEBUG_STATES      ZL5011X_CPU_BASE + 0x00080   /*  Debug States reg */

/* defines for bit fields in the registers */
/* defines for bits in the register ZL5011X_CPU_CONSTAT  */
#define ZL5011X_DMA_TX_ENABLE_BIT        0
#define ZL5011X_DMA_RX_ENABLE_BIT        1
#define ZL5011X_DMA_RX_INT_DONE_BIT      2
#define ZL5011X_DMA_RX_ALL_PKT_BIT       3
#define ZL5011X_DMA_RX_CONTINUOUS_BIT    4
#define ZL5011X_DMA_RX_INT_ALL_PKT_BIT   5
#define ZL5011X_DMA_QUEUE_ID_LSB         6

#define ZL5011X_DMA_DREQ0_DISABLE_BIT    8
#define ZL5011X_DMA_DREQ1_DISABLE_BIT    9
#define ZL5011X_DMA_GIF_RX_BUSY_BIT      10
#define ZL5011X_DMA_GIF_TX_BUSY_BIT      11

#define ZL5011X_DMA_OUT_PADDING_64       12
#define ZL5011X_DMA_OUT_PADDING_DISABLE  13

#define ZL5011X_DMA_TX_INTERRUPT_BIT     14
#define ZL5011X_DMA_RX_INTERRUPT_BIT     15

#define ZL5011X_DMA_STOP_ERROR_MASK_BIT  16
#define ZL5011X_DMA_START_ERROR_MASK_BIT 17
#define ZL5011X_DMA_STOP_ERROR_FLAG_BIT  18
#define ZL5011X_DMA_START_ERROR_FLAG_BIT 19

#define ZL5011X_DMA_DACK_SENSE           27
#define ZL5011X_DMA_DREQ_SENSE           28

/* defines for bits in the register ZL5011X_CPU_RX_SEQ_NO  */
#define ZL5011X_DMA_RX_SEQ_NUM_MASK      (Uint32T)0xffff

/* defines for bits in the register ZL5011X_CPU_RESORUCE  */
#define ZL5011X_CPU_RESOURCE_NUM_MASK    (Uint32T)0x1f

/* Definition of PTH/ PRH                                                     */
#define ZL5011X_PTH_BYTESIZE           16   /* Transmit and receive header      */
#define ZL5011X_PRH_BYTESIZE           16   /* sizes (in bytes)                 */

#define ZL5011X_PTH_WORDSIZE ZL5011X_PTH_BYTESIZE/sizeof(Uint32T)
#define ZL5011X_PRH_WORDSIZE ZL5011X_PRH_BYTESIZE/sizeof(Uint32T)

#define ZL5011X_PATHTYPE_MASK          0x001F /* 5 bits */
#define ZL5011X_PKT_LEN_MASK           0x07FF /* 11 bits */
#define ZL5011X_MP_ID_MASK             0xFFFF /* 16 bits */

#define ZL5011X_BLOCK_MASK             0x001F /* 5 bits */
#define ZL5011X_H_OFF_MASK             0x007F /* 7 bits */

#define ZL5011X_INT_DONE_MASK          0x0002 /* 1 bit */
#define ZL5011X_LAST_PKT_MASK          0x0001 /* 1 bit */

#define ZL5011X_SEQ_NO_MASK            0xFFFF /* 16 bits */
#define ZL5011X_TSTAMPCHKSUM_MASK      0xFFFF /* 16 bits */

#define ZL5011X_H_OFF                  0
#define ZL5011X_INT_DONE               0
#define ZL5011X_LAST_PKT               0

#define ZL5011X_PATHTYPE_SHIFT         27
#define ZL5011X_PKT_LEN_SHIFT          16
#define ZL5011X_MP_ID_SHIFT            0

#define ZL5011X_BLOCK_SHIFT            27
#define ZL5011X_H_OFF_SHIFT            18

#define ZL5011X_INT_DONE_SHIFT         1
#define ZL5011X_LAST_PKT_SHIFT         0

#define ZL5011X_SEQ_NO_SHIFT           16
#define ZL5011X_TSTAMPCHKSUM_SHIFT     0

#define ZL5011X_QUEUE_ID_MASK          0x0003 /* 2 bits */
#define ZL5011X_NXT_PKT_MASK           0x03FF /* 10 bits */

#define ZL5011X_QUEUE_ID_SHIFT         0
#define ZL5011X_NXT_PKT_SHIFT          0

#define ZL5011X_RX_RESOURCE_SHIFT      27
#define ZL5011X_RX_RESOURCE_MASK       0x1F /* 5 bits */

#define ZL5011X_PRH_PARITY_SHIFT       0
#define ZL5011X_PRH_PARITY_MASK        0xFFFF /* 16 bits */

/* CPQ Bypass registers bits */
#define ZL5011X_NEXT_GRANULE_PTR_SHIFT 0
#define ZL5011X_NEXT_GRANULE_PTR_MASK  0x3FFFF /* 18 bits */

#define ZL5011X_NUM_GRANULE_READ_SHIFT 18
#define ZL5011X_NUM_GRANULE_READ_MASK  0x1F    /* 5 bits */

/* GM Bypass register bits */
#define ZL5011X_GM_RLS_HEAD_SHIFT      0
#define ZL5011X_GM_RLS_HEAD_MASK       0x3FFFF /* 18 bits */
#define ZL5011X_GM_RLS_TAIL_SHIFT      0
#define ZL5011X_GM_RLS_TAIL_MASK       0x3FFFF /* 18 bits */
#define ZL5011X_GM_RLS_CNT_SHIFT       18
#define ZL5011X_GM_RLS_CNT_MASK        0x1F    /* 5 bits */

#ifdef __cplusplus
}
#endif

#endif /* ifndef _ZL5011X_CPU_MAP_H */