?? zl5011xptxmap.h
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/*******************************************************************************
*
* File name: zl5011xPtxMap.h
*
* Version: 11
*
* Author: MRC
*
* Date created: 11/04/2002
*
* Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
* All rights reserved.
*
* Module Description:
*
* This is the register definitions header file for PTX block.
* It contains the register offsets and bit field definitions.
*
* Revision History:
*
* Rev: Date: Author: Comments:
* 1 11/04/2002 MRC Creation
* 2 16/04/2002 MRC Changed Authur to Author in the header.
* 3 22/04/2002 MRC Changed the context table register bit position
* to 3, to enable address to be for 64 bit fields
* 4 22/04/2002 MRC Changed the context table mask, to ensure that
* the low 16 bits are all 0.
* 5 22/04/2002 MRC Added defines for the host entries in the
* context table
* 6 24/04/2002 MRC added defines for large and small headers
* 7 29/04/2002 MRC Changes following code review.
* 8 07/05/2002 MRC Changed enum to use uppercase
* 9 20/06/2002 MRC Updated
* 10 11/08/2002 GC Swapped l3_length position values
* 11 31/10/2002 MRC Added variants + minor fixes
*
*******************************************************************************/
#ifndef _ZL5011X_PTX_MAP_H
#define _ZL5011X_PTX_MAP_H
#ifdef __cplusplus
extern "C" {
#endif
/* addresses for the PTX registers */
#define ZL5011X_PTX_HEADER_BASE_ADDRESS ZL5011X_PTX_BASE + 0x4000
#define ZL5011X_PTX_CTRL_HEADER_BASE_ADDRESS ZL5011X_PTX_BASE + 0x6400
/* the header is 64 bytes in size */
#define ZL5011X_PTX_HEADER_SIZE 64
/* Each entry in the control header table is 8 bytes */
#define ZL5011X_PTX_CTRL_HEADER_SIZE 8
/* defines for bit fields in the registers */
/* bit positions in the first 32 bit field of the control table */
#define ZL5011X_PTX_L3_CHECKSUM_ENABLE_BIT 30
#define ZL5011X_PTX_L3_CHECKSUM_POS_BITS 24
#define ZL5011X_PTX_L2_LENGTH_VALUE_BITS 18
#define ZL5011X_PTX_L2_LENGTH_ENABLE_BIT 17
#define ZL5011X_PTX_L2_LENGTH_POS_BITS 11
#define ZL5011X_PTX_ENABLE_HEADER_BIT 8
#define ZL5011X_PTX_SRC_ADDR_FROM_MAC_BIT 7
#define ZL5011X_PTX_HEADER_LENGTH_BITS 0
#define ZL5011X_PTX_L3_CHECKSUM_POS_MASK (Uint32T)0x3f
#define ZL5011X_PTX_L2_LENGTH_VALUE_MASK (Uint32T)0x3f
#define ZL5011X_PTX_L2_LENGTH_POS_MASK (Uint32T)0x3f
#define ZL5011X_PTX_HEADER_LENGTH_MASK (Uint32T)0x7f
/* bit positions in the second 32 bit field of the header */
#define ZL5011X_PTX_L3_LENGTH_VALUE_BITS 0
#define ZL5011X_PTX_L3_LENGTH_ENABLE_BIT 6
#define ZL5011X_PTX_L3_LENGTH_POS_BITS 7
#define ZL5011X_PTX_L3_LENGTH_VALUE_MASK (Uint32T)0x3f
#define ZL5011X_PTX_L3_LENGTH_POS_MASK (Uint32T)0x3f
#ifdef __cplusplus
}
#endif
#endif
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