/*******************************************************************************
*
*  File name:              zl5011xTfmMap.h
*
*  Version:                14
*
*  Author:                 MRC
*
*  Date created:           22/02/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*
*  This is the register definitions header file for TFM block.
*  It contains the register offsets and bit field definitions.
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     22/02/2002  MRC      Creation
*  2     28/02/2002  MRC      Update
*  3     16/04/2002  MRC      Changed Authur to Author in the header
*  4     23/04/2002  MRC      Updated the revision history.
*  5     23/04/2002  MRC      Addresses changed for the registers
*  6     24/04/2002  MRC      Added bits for the cache control register
*  7     14/04/2002  MRC      The number of cache buffers changed to 3 from 5
*  8     27/06/2002  MRC      Added bits for current context switch state
*  9     22/07/2002  MRC      Update following review.
*  10    03/09/2002  KF       Changed base address of interrupt queue
*  11    31/10/2002  MRC      Added variants + minor fixes
*  12    29/05/2003  MRC      Changed bit being used to check state of the
*                             switch bit - underruns affected previous bit
*  13    29/07/2003  MRC      Added cache 1 definition
*  14    21/01/2005  MRC      Added support for restricted processor address map
*
*******************************************************************************/

#ifndef _ZL5011X_TFM_MAP_H
#define _ZL5011X_TFM_MAP_H

#ifdef __cplusplus
extern "C" {
#endif

/* addresses for the TFM registers */
#define ZL5011X_TFM_CONTEXT_LOOKUP    ZL5011X_TFM_BASE + 0x00000
#define ZL5011X_TFM_CONTEXT_MEMORY    ZL5011X_TFM_BASE + 0x02000
#define ZL5011X_TFM_CONTEXT_ERROR     ZL5011X_TFM_BASE + 0x04000
#define ZL5011X_TFM_CACHE_CTRL        ZL5011X_TFM_BASE + 0x06000
#define ZL5011X_TFM_CACHE1_FILL       ZL5011X_TFM_BASE + 0x0a000
#define ZL5011X_TFM_CACHE2_FILL       ZL5011X_TFM_BASE + 0x0c000
#define ZL5011X_TFM_CACHE5_FILL       ZL5011X_TFM_BASE + 0x12000

#ifdef _ZL5011X_RESTRICTED_ADDR_MAP

   /* queue holds the ID for a context with errors */
   #define ZL5011X_TFM_INT_ERROR_QUEUE   ZL5011X_TFM_BASE + 0x40000

   /* queue holds the ID for a context state change */
   #define ZL5011X_TFM_INT_INFO_QUEUE    ZL5011X_TFM_BASE + 0x40080

#else

   /* queue holds the ID for a context with errors */
   #define ZL5011X_TFM_INT_ERROR_QUEUE   ZL5011X_TFM_BASE + 0xF0000

   /* queue holds the ID for a context state change */
   #define ZL5011X_TFM_INT_INFO_QUEUE    ZL5011X_TFM_BASE + 0xF0080

#endif

/* defines for bit fields in the registers */

#define ZL5011X_TFM_CONTEXT_MASK         (Uint32T)0x7f

/* bit positions for ZL5011X_TFM_CONTEXT_LOOKUP register */
#define ZL5011X_TFM_LKUP_MEM_SIZE        sizeof(Uint32T)

#define ZL5011X_TFM_LKUP_CTXT_ID_BITS    0
#define ZL5011X_TFM_VALID_CHAN_BIT       16
#define ZL5011X_TFM_NEW_VALID_CHAN_BIT   17
#define ZL5011X_TFM_FIRST_CHAN_BIT       18
#define ZL5011X_TFM_NEW_FIRST_CHAN_BIT   19
#define ZL5011X_TFM_UNDERRUN_MODE_BIT    23
#define ZL5011X_TFM_UNDERRUN_BYTE_BITS   24

#define ZL5011X_TFM_UNDERRUN_BYTE_MASK   (Uint32T)0xff

/* bit positions for ZL5011X_TFM_CONTEXT_MEMORY register */
#define ZL5011X_TFM_CTXT_MEM_SIZE        sizeof(Uint32T)

#define ZL5011X_TFM_VALID_CTXT_BIT       0
#define ZL5011X_TFM_UPDATE_BIT           1
#define ZL5011X_TFM_TEARDOWN_BIT         2
#define ZL5011X_TFM_FIRST_FRAME_BIT      3
#define ZL5011X_TFM_JITTER_BUF_BITS      4
/* the interrupt bits are defined in zl5011xtfm.h, since they are used in the
   application */

#define ZL5011X_TFM_JITTER_BUF_MASK      (Uint32T)0xfffff

/* bit positions for ZL5011X_TFM_CONTEXT_ERROR register - read / clear */
#define ZL5011X_TFM_CTXT_ERR_SIZE        sizeof(Uint32T)

/* context error bits */
#define ZL5011X_TFM_UNDERRUN_ERR         0
#define ZL5011X_TFM_FRAME_ERR            1
#define ZL5011X_TFM_RELEASE_ERR          2
#define ZL5011X_TFM_LUT_ERR              3

#define ZL5011X_TFM_CONTEXT_ERR_BITS     8
#define ZL5011X_TFM_CONTEXT_ERR_MASK  (Uint32T)0xf

/* bit positions for ZL5011X_TFM_INT_ERROR_QUEUE and ZL5011X_TFM_INT_INFO_QUEUE
   registers. Each access returns the next entry on the queue */
#define ZL5011X_TFM_INT_QUEUE_CTXT_BITS  0

/* bit positions for ZL5011X_TFM_CACHE1_CTRL register */
#define ZL5011X_TFM_CACHE_CTRL_SIZE      sizeof(Uint32T)

/* set the buffers empty field to 3 and all other fields to 0 */
#define ZL5011X_TFM_CACHE_INIT_VALUE     (Uint32T)(0x3 << 9)

/* bit positions for ZL5011X_TFM_CACHE1_FILL register */
#define ZL5011X_TFM_CACHE1_FILL_SIZE     sizeof(Uint32T)

/* bit positions for ZL5011X_TFM_CACHE2_FILL register */
#define ZL5011X_TFM_CACHE2_FILL_SIZE     sizeof(Uint32T)

#define ZL5011X_TFM_PKT_LENGTH_BITS      18
#define ZL5011X_TFM_PKT_LENGTH_MASK      (Uint32T)0x7ff

/* bit positions for ZL5011X_TFM_CACHE5_FILL register */
#define ZL5011X_TFM_CACHE5_FILL_SIZE     sizeof(Uint32T)

#define ZL5011X_TFM_CTXT_SW_BIT          1

#ifdef __cplusplus
}
#endif

#endif