/*******************************************************************************
*
*  File name:              zl5011xDmaMpc8260.c
*
*  Version:                23
*
*  Author:                 ARW
*
*  Date created:           30/10/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*    This module provides the DMA interface functions for an MPC8260
*    microprocessor
*
*    This file should be used as a reference for generating low level functions
*    for other microprocessors
*
*    It is STRONGLY suggested that the Motorola MPC8260 manual is read before
*    making any changes to this file
*
*    The API software assumes there are two virtual DMA channels (0 and 1)
*    and these are mapped in this file to physical DMA channels.
*    By default channel 0 is used for CPU to device transfers and
*    channel 1 is used for device to CPU transfers
*    In the Zarlink evaluation board the mapping is as follows:
*        virtual channel 0 maps to physical IDMA 1,
*        virtual channel 1 maps to physical IDMA 2,
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     25/09/2002  ARW      New Data
*  2     17/10/2002  ARW      Peer review actions
*                             Minor bugs detected during testing on a
*                             board without a device
*  3     23/10/2002  ARW      Fixed a bug in the interrupt masking code
*  4     30/10/2002  ARW      Included uP specific structures
*  5     31/10/2002  MRC      Added variants + minor fixes
*  6     01/11/2002  ARW      Changed _DEV_BOARD to _NO_DEVICE
*  7     07/11/2002  ARW      Added port C definitions for DREQo & DREQ1
*                             Added new tasks for monitoring the IDMAs
*  8     13/11/2002  ARW      Removed printf accidently left in file
*  9     14/01/2003  ARW      Added mirco specific prototpyes and include files
*  10    31/01/2003  MRC      Moved DMA include files and micro specific
*                             prototypes to OS include file
*  11    21/03/2003  ARW      Fixed bugs found on the eval board
*  12    07/04/2003  ARW      Fixed more bugs identified during evaluation
*  13    10/04/2003  ARW      Removed _NO_DEVICE compilation code
*  14    15/04/2003  ARW      Applied byte swapping to DMA transfers
*  15    02/05/2003  ARW      Turned TRACE off in task zl5011xDmaOutOfBuffers
*  16    02/05/2003  ARW      Undid version 15 edits
*                             Removed TRACE from zl5011xDmaDetermineStatus()
*  17    29/07/2003  APL      Renamed macro _ZARLINK_ZLE5011X_BOARD
*  18    29/07/2004  MRC      Fixed some compiler warnings
*  19    03/09/2004  APL      Completely specified initialiser for IdmaMonitor
*  20    19/10/2004  APL      Added zl5011xIsDmaBufferDone and
*                                zl5011xDmaSetDescriptorInterruptFlag
*  21    16/11/2004  MRC      Shortened task label
*  22    15/04/2005  APL      Changed macros to make it easier to port to other
*                                PowerQUIC II micros
*  23    15/04/2005  APL      Fixed incorrect DACK1 mask
*
*******************************************************************************/


/*****************   INCLUDE FILES   ******************************************/
#include "zl5011x.h"
#include "zl5011xDmaMpc.h"
#include "zl5011xDmaTaskInfo.h"

/*****************   #DEFINES AND ASSOCIATED STRUCTURES    ********************/
#define ZL5011X_DMA_PADDING  ZL5011X_DMA_32BYTE_PADDING
/* MPC8260 supports bursts of 32 bytes. We need to ensure the device pads
   packets destined for the micro to integers of the transfer buffer size. This
   will ensure that the last packet does not get held up due to an incomplete
   buffer.

   The device supports 3 types of padding to suit all DMAs. This macro MUST be
   set to one of the three following values:

     ZL5011X_DMA_64BYTE_PADDING - pad packets for the CPU to be integers of 64
                                 bytes
     ZL5011X_DMA_32BYTE_PADDING - pad packets for the CPU to be integers of 32
                                 bytes
     ZL5011X_DMA_NO_PADDING     - Do not pad packets
*/

#define ZL5011X_DMA_DREQ_POLARITY ZL5011X_POSITIVE
/* Dreq line active state. This MUST be set to either:
     ZL5011X_NEGATIVE for active low, or
     ZL5011X_POSITIVE for active high                                           */

#define ZL5011X_DMA_DACK_POLARITY ZL5011X_NEGATIVE
/* Dack line active state. This MUST be set to either:
     ZL5011X_NEGATIVE for active low, or
     ZL5011X_POSITIVE for active high                                           */

#define ZL5011X_DMA_TRANSACTION_64_BIT ZL5011X_TRUE
/* The number of bits the micro uses for a transfer must be known to ensure
   packets do not get corrupted
     ZL5011X_FALSE for 32 bit transactions
     ZL5011X_TRUE for 64 bit transactions                                       */

#define ZL5011X_DMA_WRAP                0x0
/* Define a 3 bit number specifying the size of the internal buffer allocated
   in the dual port parameter RAM used for transferring packets. This number
   must be consistant with the padding capability of the device (0 gives a
   buffer size of 64 bytes, and a transfer size of 32 bytes as defined in the
   next 2 macros).                                                            */

#define ZL5011X_DMA_TRANSFER_BUFFER_SIZE (64 * (1 << ZL5011X_DMA_WRAP))
/* Using the MPC8260 formula, define the size of the internal buffer in bytes */

#define ZL5011X_DMA_MAXIMUM_TRANSFER_SIZE (ZL5011X_DMA_TRANSFER_BUFFER_SIZE -32)
/* Define the maximum transfer size the DMA_WRAP bits will provide. This value
   MUST be consistant with the padding that the device will put on packets
   destined for the CPU                                                       */

#define ZL5011X_DMA_MAX_DESCRIPTOR_COUNT 128 /* Limit a descriptor chain to one
                                             2Kbyte bank of memory. (The
                                             descriptor size is 4 words long) */

#define ZL5011X_PER_PORT_TRANSFER_SIZE    sizeof(Uint32T)
/* Transfers from the DMA internal memory to / from the device must be done a
   word at a time                                                             */

#define ZL5011X_DMA_WRAP_BIT_SHIFT        6 /* Bit shifts for ZL5011X_DMA_WRAP    */
#define ZL5011X_DPRAM_BASE_ADDRESS       64 /* Alignment (in bytes) required for
                                             the channel parameters stored in
                                             the DPRAM                        */
#define ZL5011X_DB_BASE_ADDRESS           8 /* Alignment (in bytes) required for
                                             the buffer descriptors stored in
                                             the DPRAM                        */

#define ZL5011X_CPM_MODULE_TIMEOUT       12 /* 200mS (for a 60 tick/sec CPU)    */
#define ZL5011X_IDMA_STOP_TIMEOUT        ZL5011X_CPM_MODULE_TIMEOUT
#define ZL5011X_DEVICE_STOP_TIMEOUT      12 /* Number of ticks to wait for the
  DMA to stop after issuing a stop command. On the Zarlink evaluation board 12
  ticks corresponds to 200ms.                                                 */

/* Align pointers as required                                                 */
#define ZL5011X_DMA_BUFFER_BURST_ALIGNED(buffer) (((((Uint32T)buffer-1)/ \
           zl5011xDmaProps.alignmentSize)+1)*zl5011xDmaProps.alignmentSize)

#ifdef _ZARLINK_ZLE5011X_BOARD
#define ZL5011X_DMA_NUMBER_OF_CHANNELS    2 /* Number of independent DMA channels
                                             in the MPC8260 bound that can be
                                             used in the eval board           */

/* The following macros connect IDMA channel 1 and 2 DREQ and DACK signals
   to the external world. This is micro and board specific.
   In the Zarlink eval board port C pins 0 (DREQ1), 1 (DREQ2), 23 (DACK1)
   and 3 (DACK2) are used       */
#define PPC8260_PORTC_DREQ1_MASK   0x80000000
#define PPC8260_PORTC_DACK1_MASK   0x00000100
#define PPC8260_PORTC_DREQ2_MASK   0x40000000
#define PPC8260_PORTC_DACK2_MASK   0x10000000

#define PPC8260_IMM_PIO_PSORC 0x10D48
#define PPC8260_IMM_PIO_PPARC 0x10D44
#define PPC8260_IMM_PIO_PDIRC 0x10D40
#define PPC8260_IMM_CPM_RCCR  0x119C4

#define PPC8260_IMM_CPM_CMD_1  0x00A00000     /* IDMA 1, level sensitive, priority option 3 */
#define PPC8260_IMM_CPM_CMD_2  0x00410000     /* IDMA 2, level sensitive, priority option 2 */

#else
#define ZL5011X_DMA_NUMBER_OF_CHANNELS    4 /* Number of independent DMA channels
                                             in the MPC8260                   */

#endif

/******************************************************************************/
/* IDMA Event (IDSR) & Mask (IDMR) registers bit fields                       */
#define PPC8260_IMM_IDSR             0x11020 /* IDMA registers base           */
#define PPC8260_IMM_IDSR_INC         0x00008 /* Increment value for IDSR regs
                                                (1 per DMA channel)           */

/* IDSR/IDMR bit fields                                                       */
#define PPC8260_IDMA_IDSR_BC         0x01    /* Buffer descriptor completed   */
#define PPC8260_IDMA_IDSR_EDN        0x02    /* Channel terminated transfer due
                                                to external signal            */
#define PPC8260_IDMA_IDSR_OB         0x04    /* No valid BDs left to transfer */
#define PPC8260_IDMA_IDSR_SC         0x08    /* Stop completed                */

/******************************************************************************/
/* IDMA parameter ram bit fields                                              */
#define PPC8260_IMM_IDMA_BASE         0x87FE /* Base address for IDMA params  */
#define PPC8260_IMM_IDMA_BASE_INC     0x0100 /* Increment value for each DMA
                                                channel                       */

/* Bit fields for DCM word                                                    */
#define PPC8260_IDMA_SINC            0x0020
#define PPC8260_IDMA_DINC            0x0010
#define PPC8260_IDMA_SD_MEM_MEM      0x0000
#define PPC8260_IDMA_SD_MEM_PER      0x0001
#define PPC8260_IDMA_SD_PER_MEM      0x0002
#define PPC8260_IDMA_ERM             0x0008 /* External request mode          */
#define PPC8260_IDMA_DT              0x0004
#define PPC8260_IDMA_FB_MODE         0x8000

/******************************************************************************/
/* Communications Processor Module                                            */
#define PPC8260_IMM_CPM_CPCR         0x119C0 /* CPM command register          */

#define PPC8260_CPM_BUSY          0x00010000 /* CPM busy bit                  */
#define PPC8260_CPM_IDMA_START    0x1E810009 /* CPM command to start IDMA1    */
#define PPC8260_CPM_IDMA_STOP     0x1E81000B /* CPM command to stop IDMA1     */
#define PPC8260_CPM_COMMAND_INC   0x04200000 /* Increment number to apply to
                                                start and stop commands for
                                                another DMA channel           */

/******************************************************************************/
/* Buffer descriptor definition - Bit fields for ctlsts word decribing how to
   perform the data transfer                                                  */
#define PPC8260_IDMA_BD_SDTB_60X  0x00000000
#define PPC8260_IDMA_BD_DDTB_60X  0x00000000
#define PPC8260_IDMA_BD_SDTB_LCL  0x00000200
#define PPC8260_IDMA_BD_DDTB_LCL  0x00010000
#define PPC8260_IDMA_BD_DBO_PPC   0x00080000 /* DMA to perform byte swapping  */
#define PPC8260_IDMA_BD_SBO_PPC   0x00000800 /* in both directions            */
#define PPC8260_IDMA_BD_VALID     0x80000000
#define PPC8260_IDMA_BD_WRAP      0x20000000
#define PPC8260_IDMA_BD_INT       0x10000000
#define PPC8260_IDMA_BD_LAST      0x08000000
#define PPC8260_IDMA_BD_CM        0x02000000
#define PPC8260_IDMA_BD_SDN       0x00400000
#define PPC8260_IDMA_BD_DDN       0x00200000

/*****************   DATA STRUCTURES   ****************************************/
/* IDMA Event (IDSR) & Mask (IDMR) registers                                  */
typedef struct zl5011xDmaRegistersS
{
  volatile Uint8T  idsr;
           Uint8T  reserved1;
           Uint8T  reserved2;
           Uint8T  reserved3;
  volatile Uint8T  idmr;
} zl5011xDmaRegistersS;

/* IDMA parameter ram structure for register addresses in correct offset
   positions                                                                  */
typedef struct zl5011xDmaParametersS
{
  volatile Uint16T ibase;
  volatile Uint16T dcm;
  volatile Uint16T ibdptr;
  volatile Uint16T dpr_buf;
  volatile Uint16T buf_inv;
  volatile Uint16T ss_max;
  volatile Uint16T dpr_in_ptr;
  volatile Uint16T sts;
  volatile Uint16T dpr_out_ptr;
  volatile Uint16T seob;
  volatile Uint16T deob;
  volatile Uint16T dts;
  volatile Uint16T ret_add;
           Uint16T reserved1;
  volatile Uint32T bd_cnt;
  volatile Uint32T s_ptr;
  volatile Uint32T d_ptr;
  volatile Uint32T istate;
} zl5011xDmaParametersS;

/* Buffer descriptor definition                                               */
typedef struct zl5011xDmaBufferDescripS
{
  volatile Uint32T ctlsts;
  volatile Uint32T length;
  volatile Uint32T source;
  volatile Uint32T destination;
} zl5011xDmaBufferDescripS;

/* Structure defining all micro specific parameters                           */
typedef struct zl5011xDmaStructS
{
   zl5011xDmaRegistersS *reg;            /* Status and mask registers          */
   zl5011xDmaParametersS *params;        /* DMA chhanel parameters             */
   zl5011xDmaBufferDescripS *bufferDescrip;
} zl5011xDmaStructS;

/* Structure used by the IDMA task for monitoring the status of the IDMA
   channels                                                                   */
typedef struct zl5011xIdmaMonitorS
{
    zl5011xBooleanE channelEnabled[ZL5011X_DMA_NUMBER_OF_CHANNELS];
    Uint32T taskId;
    zl5011xBooleanE goFlag;
    zl5011xDmaChannelS *dmaChannel[ZL5011X_DMA_NUMBER_OF_CHANNELS];
} zl5011xIdmaMonitorS;

/*****************   ENUMERATIONS    ******************************************/


/*****************   STATIC FUNCTION DECLARATIONS   ***************************/
static void zl5011xDmaOutOfBuffers(void);

static void zl5011xassignDmaPorts(zl5011xDmaChannelS *dmaChannel);

static void zl5011xConnectDreq(zl5011xDmaChannelS *dmaChannel);

static void zl5011xDisconnectDreq(zl5011xDmaChannelS *dmaChannel);

/*****************   STATIC GLOBAL VARIABLES   ********************************/

/*****************   EXPORTED GLOBAL VARIABLES   ******************************/
/* Global structure for storing all global DMA parameters, and setting the
   device needs to have in order to work with the DMA                         */
zl5011xDmaPropertiesS zl5011xDmaProps = {
    ZL5011X_DMA_NUMBER_OF_CHANNELS,
    ZL5011X_DMA_MAX_DESCRIPTOR_COUNT,
    ZL5011X_DMA_PADDING,
    ZL5011X_DMA_DREQ_POLARITY,
    ZL5011X_DMA_DACK_POLARITY,
    ZL5011X_DEVICE_STOP_TIMEOUT,
    ZL5011X_DMA_MAXIMUM_TRANSFER_SIZE,
    ZL5011X_DMA_TRANSFER_BUFFER_SIZE,
    ZL5011X_DMA_TRANSACTION_64_BIT};

/* A global structure has been defined to store all microspecific data required
   to program the DMA. An instance of the structure is needed for both transmit
   and receive.

   The MPC8260 requires a structure containing three pointers representing the
   three areas of the dual port parameter RAM that needs to be accessed:
       - Set/Read the control registers
       - Define the parameters for each DMA channel
       - Define a chain of buffer descriptors for each channel                */
static zl5011xDmaStructS TxRamPtrs = {NULL, NULL, NULL};
static zl5011xDmaStructS RxRamPtrs = {NULL, NULL, NULL};

#ifdef _ZARLINK_ZLE5011X_BOARD
static zl5011xIdmaMonitorS IdmaMonitor =
                  {
                     {ZL5011X_FALSE,ZL5011X_FALSE},
                     OS_ERROR,