{
      countValue = ZL5011X_DPLL_MAX_INVERSE_VALUE /
            (zl5011xParams->wanIf.clock.sync.dpllCentreCount / 2);

      status = zl5011xWrite(zl5011xParams, ZL5011X_DPLL_INVERSE_CENTRE_FREQ,
            countValue << ZL5011X_DPLL_INVERSE_CENTRE_BITS);
   }
   else
   {
      status = ZL5011X_ERROR;
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetT1InverseFreq

 Description:
    The inverse of the T1 reference frequency is required by the DPLL

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetT1InverseFreq(zl5011xParamsS *zl5011xParams)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T countValue;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetT1InverseFreq:", 0, 0, 0, 0, 0, 0);

   /* the calculation used to determine the inverse frequency is :-
         REAL_MAX_INVERSE_VALUE / T1 center frequency
      However, the maximum number is larger than a 32 bit integer, so the divide
      is done in two stages :-
         MAX_INVERSE_VALUE / (T1 center frequency / 2)
      where MAX_INVERSE_VALUE = (REAL_MAX_INVERSE_VALUE / 2) */
   countValue = (ZL5011X_DPLL_MAX_INVERSE_VALUE / ZL5011X_DPLL_INVERSE_T1_DIV) *
         ZL5011X_DPLL_INVERSE_T1_MULT;

   if ((zl5011xParams->wanIf.clock.sync.dpllCentreCount / 2) != 0)
   {
      countValue /= zl5011xParams->wanIf.clock.sync.dpllCentreCount / 2;

      status = zl5011xWrite(zl5011xParams, ZL5011X_DPLL_INVERSE_T1_FREQ,
            countValue << ZL5011X_DPLL_INVERSE_T1_BITS);
   }
   else
   {
      status = ZL5011X_ERROR;
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetJ2InverseFreq

 Description:
    The inverse of the J2 reference frequency is required by the DPLL

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetJ2InverseFreq(zl5011xParamsS *zl5011xParams)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T countValue;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetJ2InverseFreq:", 0, 0, 0, 0, 0, 0);

   /* the calculation used to determine the inverse frequency is :-
         REAL_MAX_INVERSE_VALUE / J2 center frequency
      However, the maximum number is larger than a 32 bit integer, so the divide
      is done in two stages :-
         MAX_INVERSE_VALUE / (J2 center frequency / 2)
      where MAX_INVERSE_VALUE = (REAL_MAX_INVERSE_VALUE / 2) */
   countValue = (ZL5011X_DPLL_MAX_INVERSE_VALUE / ZL5011X_DPLL_INVERSE_J2_DIV) *
         ZL5011X_DPLL_INVERSE_J2_MULT;

   if ((zl5011xParams->wanIf.clock.sync.dpllCentreCount / 2) != 0)
   {
      countValue /= zl5011xParams->wanIf.clock.sync.dpllCentreCount / 2;

      status = zl5011xWrite(zl5011xParams, ZL5011X_DPLL_INVERSE_J2_FREQ,
            countValue << ZL5011X_DPLL_INVERSE_J2_BITS);
   }
   else
   {
      status = ZL5011X_ERROR;
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetLockRange

 Description:
    This programs the count value that the DPLL frequency can deviate from the
    centre. The count value is calculated, based on the centre frequency
    for the DPLL

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   maxOffsetPpm   maximum offset that the DPLL frequency can move by in ppm.

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetLockRange(zl5011xParamsS *zl5011xParams, Uint32T maxOffsetPpm)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T lockValue;
   Uint32T bits;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetLockRange:", 0, 0, 0, 0, 0, 0);

   if (maxOffsetPpm > ZL5011X_DPLL_MAX_LOCK_RANGE_PPM)
   {
      status = ZL5011X_PARAMETER_INVALID;
   }

   if (status == ZL5011X_OK)
   {
      lockValue = (maxOffsetPpm * (zl5011xParams->wanIf.clock.sync.dpllCentreCount / 1000)) / 1000;

      if ((lockValue & ~ZL5011X_DPLL_LOCK_RANGE_MASK) != 0)
      {
         status = ZL5011X_PARAMETER_INVALID;
      }
   }

   if (status == ZL5011X_OK)
   {
      ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetLockRange: %u",
            lockValue, 0, 0, 0, 0, 0);

      zl5011xParams->wanIf.clock.sync.dpllLockRange = maxOffsetPpm;

      bits = (lockValue & ZL5011X_DPLL_LOCK_RANGE_MASK) << ZL5011X_DPLL_LOCK_RANGE_BITS;

      status = zl5011xWrite(zl5011xParams, ZL5011X_DPLL_LOCK_RANGE, bits);
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetLockDetectThreshold

 Description:
    Sets the threshold to be used to determine whether the DPLL is locked.

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   detectThreshold   maximum phase offset for the DPLL to be deemed in lock.
                     In UI (unit interval) x 10. i.e. 20 means that the DPLL
                     is in lock if up to 2.0 clock cycles of the DPLL reference
                     input adrift.
   detectTimeUs   time that the DPLL deviation must be below the threshold in
                  order to declare lock.

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetLockDetectThreshold(zl5011xParamsS *zl5011xParams,
   Uint16T detectThreshold, Uint32T detectTimeUs)
{
   zlStatusE status = ZL5011X_OK;
   Uint16T temp;
   Uint32T bits;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID,
         "zl5011xPacDpllSetLockDetectThreshold: threshold %d, time ms %d",
         detectThreshold, detectTimeUs, 0, 0, 0, 0);

   if (status == ZL5011X_OK)
   {
      /* convert the time in Us into the value required in the device - which
         is in frames. So divide by 125 (1 frame = 125us) */
      temp = (Uint16T)(detectTimeUs / 125);
   }

   if (status == ZL5011X_OK)
   {
      bits = (detectThreshold << ZL5011X_DPLL_LOCK_THRESHOLD_BITS) |
            (temp << ZL5011X_DPLL_LOCK_TIME_BITS);

      status = zl5011xWrite(zl5011xParams, ZL5011X_DPLL_LOCK_DETECT, bits);

      zl5011xParams->wanIf.clock.sync.dpllLockDetectThreshold = detectThreshold;
      zl5011xParams->wanIf.clock.sync.dpllLockDetectTimeUs = detectTimeUs;
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetSlewRate

 Description:
    This programs the maximum slew rate for the DPLL frequency and the DPLL
    bandwidth.

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   slewRate       a number that is used to control the slew rate.
   dpllBandwidth  controls the bandwith of the DPLL

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
   The value passed in to this function must take account of the system
   clock etc.

*******************************************************************************/

zlStatusE zl5011xPacDpllSetSlewRate(zl5011xParamsS *zl5011xParams, Uint32T slewRate,
      Uint8T dpllBandwidth)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T bits;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID,
         "zl5011xPacDpllSetSlewRate: slew %d, bandwidth %d",
         slewRate, dpllBandwidth, 0, 0, 0, 0);

   if ((slewRate & ~ZL5011X_DPLL_SLEW_RATE_MASK) != 0)
   {
      status = ZL5011X_PARAMETER_INVALID;
   }

   if ((dpllBandwidth & ~ZL5011X_DPLL_BANDWIDTH_CTRL_MASK) != 0)
   {
      status = ZL5011X_PARAMETER_INVALID;
   }

   if (status == ZL5011X_OK)
   {
      bits = (slewRate << ZL5011X_DPLL_SLEW_RATE_BITS) |
            (dpllBandwidth << ZL5011X_DPLL_BANDWIDTH_CTRL_BITS);

      status = zl5011xWrite(zl5011xParams,
            ZL5011X_DPLL_SLEW_RATE, bits);

      zl5011xParams->wanIf.clock.sync.dpllSlewRate = slewRate;
      zl5011xParams->wanIf.clock.sync.dpllBandwidth = dpllBandwidth;
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetRefPriority

 Description:
    Sets the priority of the reference sources for the DPLL. The can restrict
    the DPLL to using only one of the references, give priority to one over the
    other or give priority to the reference currently in use.

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   priority       sets the priority of the reference sources

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetRefPriority(zl5011xParamsS *zl5011xParams,
      zl5011xDpllRefPriorityE priority)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T bits, bitMask;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetRefPriority: %d", priority, 0, 0, 0, 0, 0);

   status = ZL5011X_CHECK_DPLL_PRIORITY(priority);

   if (status == ZL5011X_OK)
   {
      bits = priority << ZL5011X_DPLL_REF_PRIORITY_BITS;
      bitMask = ZL5011X_DPLL_REF_PRIORITY_MASK << ZL5011X_DPLL_REF_PRIORITY_BITS;

      zl5011xParams->wanIf.clock.sync.priority = priority;

      status = zl5011xReadModWrite(zl5011xParams,
            ZL5011X_DPLL_CHANGE_CONTROL, bits, bitMask);
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetClockMode

 Description:
    Sets the operating mode of the DPLL. This would only be used in normal mode,
    but has a routine to provide access for completeness.

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   mode           sets the mode of operation of the DPLL.

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetClockMode(zl5011xParamsS *zl5011xParams,
      zl5011xDpllOperationE mode)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T bits, bitMask;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetClockMode: %d", mode, 0, 0, 0, 0, 0);

   status = ZL5011X_CHECK_DPLL_MODE(mode);

   if (status == ZL5011X_OK)
   {
      bits = mode << ZL5011X_DPLL_FORCE_MODE_BITS;
      bitMask = (ZL5011X_DPLL_FORCE_MODE_MASK << ZL5011X_DPLL_FORCE_MODE_BITS);

      status = zl5011xReadModWrite(zl5011xParams,
            ZL5011X_DPLL_CHANGE_CONTROL, bits, bitMask);
   }

   return(status);
}

/*******************************************************************************

 Function:
    zl5011xPacDpllSetMtieMode

 Description:
    The DPLL can be set to adjust the phase of a reference source during a
    reference switch. This function is used to enable / disable this feature.
    This function also sets the length of half a bit period, which is required
    for the MTIE function.

 Inputs:
   zl5011xParams   Pointer to the structure for this device instance
   mtie           ZL5011X_TRUE if phase changes should be made during reference
                  switching

 Outputs:
    None

 Returns:
   zlStatusE

 Remarks:
    None

*******************************************************************************/

zlStatusE zl5011xPacDpllSetMtieMode(zl5011xParamsS *zl5011xParams, zl5011xBooleanE mtie)
{
   zlStatusE status = ZL5011X_OK;
   Uint32T bits = 0, bitMask = 0;
   Uint32T halfRefPeriod;

   ZL5011X_TRACE(ZL5011X_PAC_FN_ID, "zl5011xPacDpllSetMtieMode: %d", mtie, 0, 0, 0, 0, 0);

   status = ZL5011X_CHECK_BOOLEAN(mtie);

   if (status == ZL5011X_OK)
   {
      /* work out how many system clock periods there are in half of a
         DPLL reference input period */
      halfRefPeriod = zl5011xParams->systemClockFreq /
            (zl5011xParams->wanIf.clock.sync.refInputFreqHz * 2);

      if ((halfRefPeriod & ~ZL5011X_DPLL_MTIE_ROUND_OFF_MASK) != 0)
      {