/* zxr10_motTsecEnd.h - zxr10_motorola TSEC Ethernet network interface.*//* Copyright 2003-2004 Wind River Systems, Inc. *//*modification history--------------------01i,23nov04,pmr  fix for large pings at gigabit speed.01h,19nov04,pmr  SPR 104443 - back-ported bug fixes from VxWorks 6.0 version01g,22oct04,dtr  Added Interrupt coalescing defines. Changed some defaults                 for increased performance.SPR 10253601f,22jul04,rcs  Added PHY Access definitions01e,21jun04,mil  Changed cacheArchXXX funcs to cacheXXX funcs.01d,27apr04,mdo  Latest updates for B6 build01c,13apr04,mil  Fixed location of header file.01c,26mar04,rcs  Fixed SPR 9543201b,12feb04,rcs  Adjusted default settings01b,04feb04,mil  Fixed problem if compiled with GNU.01a,10mar03,gjc  zxr10_motorola TSEC Ethernet.*/#ifndef __INCzxr10_motTsecEndh#define __INCzxr10_motTsecEndh/* includes */#ifdef __cplusplusextern "C" {#endif/*#include "etherLib.h"#include "miiLib.h"*/#include "virPhy.h"#include "Driver/drvLib/include/drv_comm.h"typedef struct ether_addr ENET_ADDR;#define ZXR10_MOT_TSEC_DBG		1#define ZXR10_MOT_TSEC_DEV_NAME        "mottsec"#define ZXR10_MOT_TSEC_DEV_NAME_LEN    8#define ZXR10_MOT_TSEC_MAX_DEVS        2#define ZXR10_MOT_TSEC_DEV_1           0#define ZXR10_MOT_TSEC_DEV_2           1#define ZXR10_MOT_TSEC_ADRS_OFFSET_1  0x00024000#define ZXR10_MOT_TSEC_ADRS_OFFSET_2  0x00025000/* IEVENT and IMASK Register definitions */#define ZXR10_MOT_TSEC_IEVENT_BABR    0x80000000#define ZXR10_MOT_TSEC_IEVENT_RXC     0x40000000#define ZXR10_MOT_TSEC_IEVENT_BSY     0x20000000#define ZXR10_MOT_TSEC_IEVENT_EBERR   0x10000000#define ZXR10_MOT_TSEC_IEVENT_MSRO    0x04000000#define ZXR10_MOT_TSEC_IEVENT_GTSC    0x02000000#define ZXR10_MOT_TSEC_IEVENT_BABT    0x01000000#define ZXR10_MOT_TSEC_IEVENT_TXC     0x00800000#define ZXR10_MOT_TSEC_IEVENT_TXE     0x00400000#define ZXR10_MOT_TSEC_IEVENT_TXB     0x00200000#define ZXR10_MOT_TSEC_IEVENT_TXF     0x00100000#define ZXR10_MOT_TSEC_IEVENT_LC      0x00040000#define ZXR10_MOT_TSEC_IEVENT_CRL     0x00020000#define ZXR10_MOT_TSEC_IEVENT_XFUN    0x00010000#define ZXR10_MOT_TSEC_IEVENT_RXB0    0x00008000#define ZXR10_MOT_TSEC_IEVENT_GRSC    0x00000100#define ZXR10_MOT_TSEC_IEVENT_RXF0    0x00000080/* Error Disable Registers */#define ZXR10_MOT_TSEC_EDIS_BSYDIS    0x20000000#define ZXR10_MOT_TSEC_EDIS_EBERRDIS  0x10000000#define ZXR10_MOT_TSEC_EDIS_TXEDIS    0x00400000#define ZXR10_MOT_TSEC_EDIS_LCDIS     0x00040000#define ZXR10_MOT_TSEC_EDIS_CRLDIS    0x00020000#define ZXR10_MOT_TSEC_EDIS_XFUNDIS   0x00010000/* Ethernet Control Register */#define ZXR10_MOT_TSEC_ECNTRL_CLRCNT  0x00004000#define ZXR10_MOT_TSEC_ECNTRL_AUTOZ   0x00002000#define ZXR10_MOT_TSEC_ECNTRL_STEN    0x00001000#define ZXR10_MOT_TSEC_ECNTRL_TBIM    0x00000020#define ZXR10_MOT_TSEC_ECNTRL_RPM     0x00000010#define ZXR10_MOT_TSEC_ECNTRL_R100M   0x00000008/* Minimum Frame Register Length */#define ZXR10_MOT_TSEC_MINFLR(l)      (l&0x0000007f)/* PTV Register Definition */#define ZXR10_MOT_TSEC_PTV_PTE(t)     (t<<16)#define ZXR10_MOT_TSEC_PTV_PT(t)      (t)/* DMA Control Register */#define ZXR10_MOT_TSEC_DMACTRL_TDSEN  0x00000080#define ZXR10_MOT_TSEC_DMACTRL_TBDSEN 0x00000040#define ZXR10_MOT_TSEC_DMACTRL_GRS    0x00000010#define ZXR10_MOT_TSEC_DMACTRL_GTS    0x00000008#define ZXR10_MOT_TSEC_DMACTRL_TOD    0x00000004#define ZXR10_MOT_TSEC_DMACTRL_WWR    0x00000002#define ZXR10_MOT_TSEC_DMACTRL_WOP    0x00000001/* TBI Physical Address Registers */#define ZXR10_MOT_TSEC_TBIPA(a)           (a&0x0000001f)/* FIFO Transmit Threshold Registers */#define ZXR10_MOT_TSEC_FIFO_TX_THR(a)     (a&0x000001ff)/* FIFO Transmit Starve Registers */#define ZXR10_MOT_TSEC_FIFO_TX_STARVE(a)  (a&0x000001ff)/* FIFO Transmit Starve Shutoff Registers */#define ZXR10_MOT_TSEC_FIFO_TX_STARVE_SHUTOFF(a) (a&0x000001ff)/* Transmit Control Register */#define ZXR10_MOT_TSEC_TCTRL_THDF         0x00000800#define ZXR10_MOT_TSEC_TCTRL_RFC_PAUSE    0x00000010#define ZXR10_MOT_TSEC_TCTRL_TFC_PAUSE    0x00000008#define ZXR10_MOT_TSEC_TSTAT_THLT     0x80000000/* Transmit Interrupt Coalescing */#define ZXR10_MOT_TSEC_TXIC_ICEN	0x80000000#define ZXR10_MOT_TSEC_TXIC_ICFCT(a)  ((a&0x000000ff)<<21)#define ZXR10_MOT_TSEC_TXIC_ICTT(a)   (a&0x0000ffff)#define ZXR10_MOT_TSEC_OSTBD_R        0x80000000#define ZXR10_MOT_TSEC_OSTBD_PAD      0x40000000#define ZXR10_MOT_TSEC_OSTBD_W        0x20000000#define ZXR10_MOT_TSEC_OSTBD_I        0x10000000#define ZXR10_MOT_TSEC_OSTBD_L        0x08000000#define ZXR10_MOT_TSEC_OSTBD_TC       0x04000000#define ZXR10_MOT_TSEC_OSTBD_DEF      0x02000000#define ZXR10_MOT_TSEC_OSTBD_LC       0x00800000#define ZXR10_MOT_TSEC_OSTBD_RL       0x00400000#define ZXR10_MOT_TSEC_OSTBD_RC(r)    ((r&0x0000003c)>>18)#define ZXR10_MOT_TSEC_OSTBD_UN       0x00020000#define ZXR10_MOT_TSEC_OSTBD_LEN(l)   (l&0x0000ffff)#define ZXR10_MOT_TSEC_RCTRL_BC_REJ   0x00000010#define ZXR10_MOT_TSEC_RCTRL_PROM     0x00000008#define ZXR10_MOT_TSEC_RCTRL_RSF      0x00000004#define ZXR10_MOT_TSEC_RSTAT_QHLT     0x00800000#define ZXR10_MOT_TSEC_TDLEN(l)       (l&0x0000ffff)#define ZXR10_MOT_TSEC_RBDLEN(l)      (l&0x0000ffff)#define ZXR10_MOT_TSEC_CRBPTR(p)      (p&0xfffffff8)#define ZXR10_MOT_TSEC_MRBLR(l)       (l&0x0000ffc0)#define ZXR10_MOT_TSEC_RBASE(p)       (p&0xfffffff8)#define ZXR10_MOT_TSEC_MACCFG1_SOFT_RESET     0x80000000#define ZXR10_MOT_TSEC_MACCFG1_RESET_RX_MC    0x00080000#define ZXR10_MOT_TSEC_MACCFG1_RESET_TX_MC    0x00040000#define ZXR10_MOT_TSEC_MACCFG1_RESET_RX_FUN   0x00020000#define ZXR10_MOT_TSEC_MACCFG1_RESET_TX_FUN   0x00010000#define ZXR10_MOT_TSEC_MACCFG1_LOOPBACK       0x00000100#define ZXR10_MOT_TSEC_MACCFG1_RX_FLOW        0x00000020#define ZXR10_MOT_TSEC_MACCFG1_TX_FLOW        0x00000010#define ZXR10_MOT_TSEC_MACCFG1_SYNCD_RX_EN    0x00000008#define ZXR10_MOT_TSEC_MACCFG1_RX_EN          0x00000004#define ZXR10_MOT_TSEC_MACCFG1_SYNCD_TX_EN    0x00000002#define ZXR10_MOT_TSEC_MACCFG1_TX_EN          0x00000001#define ZXR10_MOT_TSEC_MACCFG2_PRE_LEN(l)         ((l<<12) & 0xf000)#define ZXR10_MOT_TSEC_MACCFG2_PRE_LEN_GET(r)     ((r&0xf000)>>12)#define ZXR10_MOT_TSEC_MACCFG2_IF_MODE(m)         ((m<<8) & 0x0300)#define ZXR10_MOT_TSEC_MACCFG2_IF_MODE_GET(r)     ((r&0x0300)>>8)#define ZXR10_MOT_TSEC_MACCFG2_IF_MODE_MASK       0x00000003#define ZXR10_MOT_TSEC_MACCFG2_IF_MODE_MII        0x00000001#define ZXR10_MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI   0x00000002#define ZXR10_MOT_TSEC_MACCFG2_HUGE_FRAME         0x00000020#define ZXR10_MOT_TSEC_MACCFG2_LENGTH_CHECK       0x00000010#define ZXR10_MOT_TSEC_MACCFG2_PADCRC             0x00000004#define ZXR10_MOT_TSEC_MACCFG2_CRC_EN             0x00000002#define ZXR10_MOT_TSEC_MACCFG2_FULL_DUPLEX        0x00000001#define ZXR10_MOT_TSEC_IPGIFG_NBBIPG1(l)      ((l&0x0000007f)<<24)#define ZXR10_MOT_TSEC_IPGIFG_NBBIPG2(l)      ( (l&0x0000007f)<<16)#define ZXR10_MOT_TSEC_IPGIFG_MIFGE(l)        ((l&0x000000ff)<<8)#define ZXR10_MOT_TSEC_IPGIFG_BBIPG(l)        (l&0x0000007f)#define ZXR10_MOT_TSEC_HALDUP_ALTBEB_TRUNC(l) ((l&0x0000000f)<<20)#define ZXR10_MOT_TSEC_HALFDUP_BEB            0x00080000#define ZXR10_MOT_TSEC_HALFDUP_BPNBO          0x00040000#define ZXR10_MOT_TSEC_HALFDUP_NBO            0x00020000#define ZXR10_MOT_TSEC_HALFDUP_EXCESS_DEF     0x00010000#define ZXR10_MOT_TSEC_HALDUP_RETRY(v)        ((v&0x0000000F)<<12)#define ZXR10_MOT_TSEC_HALDUP_COL_WINDOW(w)   (w&0x003f)#define ZXR10_MOT_TSEC_MAXFRM(l)              (l&0x0000ffff)#define ZXR10_MOT_TSEC_MIIMCFG_RESET          0x80000000#define ZXR10_MOT_TSEC_MIIMCFG_NO_PRE         0x00000010#define ZXR10_MOT_TSEC_MIIMCFG_MCS(l)         (l&0x00000007)#define ZXR10_MOT_TSEC_MIIMCFG_MCS_2          0x00000000#define ZXR10_MOT_TSEC_MIIMCFG_MCS_4          0x00000001#define ZXR10_MOT_TSEC_MIIMCFG_MCS_6          0x00000002#define ZXR10_MOT_TSEC_MIIMCFG_MCS_8          0x00000003#define ZXR10_MOT_TSEC_MIIMCFG_MCS_10         0x00000004#define ZXR10_MOT_TSEC_MIIMCFG_MCS_14         0x00000005#define ZXR10_MOT_TSEC_MIIMCFG_MCS_20         0x00000006#define ZXR10_MOT_TSEC_MIIMCFG_MCS_28         0x00000007#define ZXR10_MOT_TSEC_MIIMCOM_SCAN_CYCLE     0x00000002#define ZXR10_MOT_TSEC_MIIMCOM_READ_CYCLE     0x00000001#define ZXR10_MOT_TSEC_MIIMADD_PHYADRS(a)     ((a&0x0000001f)<<8)#define ZXR10_MOT_TSEC_MIIMADD_REGADRS(a)     (a&0x0000001f)#define ZXR10_MOT_TSEC_MIIMCON_PHY_CTRL(a)    (a&0x0000ffff)#define ZXR10_MOT_TSEC_MIIMSTAT_PHY(a)        (a&0x0000ffff)#define ZXR10_MOT_TSEC_MIIMIND_NOT_VALID      0x00000004#define ZXR10_MOT_TSEC_MIIMIND_SCAN           0x00000002#define ZXR10_MOT_TSEC_MIIMIND_BUSY           0x00000001#define ZXR10_MOT_TSEC_IFSTAT_EXCESS_DEF      0x00000200#define ZXR10_MOT_TSEC_MACSTNADDR1_SA_1       0xff000000#define ZXR10_MOT_TSEC_MACSTNADDR1_SA_2       0x00ff0000#define ZXR10_MOT_TSEC_MACSTNADDR1_SA_3       0x0000ff00#define ZXR10_MOT_TSEC_MACSTNADDR1_SA_4       0x000000ff#define ZXR10_MOT_TSEC_MACSTNADDR2_SA_5       0xff000000#define ZXR10_MOT_TSEC_MACSTNADDR2_SA_6       0x00ff0000/* Transmit Buffer Descriptor bit definitions */#define ZXR10_MOT_TSEC_TBD_R          0x8000#define ZXR10_MOT_TSEC_TBD_PADCRC     0x4000#define ZXR10_MOT_TSEC_TBD_W          0x2000#define ZXR10_MOT_TSEC_TBD_I          0x1000#define ZXR10_MOT_TSEC_TBD_L          0x0800#define ZXR10_MOT_TSEC_TBD_TC         0x0400#define ZXR10_MOT_TSEC_TBD_DEF        0x0200#define ZXR10_MOT_TSEC_TBD_HFE_LC     0x0080#define ZXR10_MOT_TSEC_TBD_HFE_RL     0x0040#define ZXR10_MOT_TSEC_TBD_HFE_RC     0x003c#define ZXR10_MOT_TSEC_TBD_HFE_UN     0x0002/* Receive Buffer Descriptors bit definitions */#define ZXR10_MOT_TSEC_RBD_E          0x8000#define ZXR10_MOT_TSEC_RBD_RO1        0x4000#define ZXR10_MOT_TSEC_RBD_W          0x2000#define ZXR10_MOT_TSEC_RBD_I          0x1000#define ZXR10_MOT_TSEC_RBD_L          0x0800#define ZXR10_MOT_TSEC_RBD_F          0x0400#define ZXR10_MOT_TSEC_RBD_M          0x0200#define ZXR10_MOT_TSEC_RBD_BC         0x0080#define ZXR10_MOT_TSEC_RBD_MC         0x0040#define ZXR10_MOT_TSEC_RBD_LG         0x0020#define ZXR10_MOT_TSEC_RBD_NO         0x0010#define ZXR10_MOT_TSEC_RBD_SH         0x0008#define ZXR10_MOT_TSEC_RBD_CR         0x0004#define ZXR10_MOT_TSEC_RBD_OV         0x0002#define ZXR10_MOT_TSEC_RBD_TR         0x0001#define ZXR10_MOT_TSEC_RBD_ERR  (ZXR10_MOT_TSEC_RBD_TR | ZXR10_MOT_TSEC_RBD_OV |  \                           ZXR10_MOT_TSEC_RBD_CR | ZXR10_MOT_TSEC_RBD_SH |  \                           ZXR10_MOT_TSEC_RBD_NO | ZXR10_MOT_TSEC_RBD_LG)#define ZXR10_MOT_TSEC_ATTR_ELCWT_NA       0x0#define ZXR10_MOT_TSEC_ATTR_ELCWT_L2       0x4#define ZXR10_MOT_TSEC_ATTR_ELCWT_L2_LOCK  0x6#define ZXR10_MOT_TSEC_ATTR_ELCWT(v)       ((v&0x00000003)<<13)#define ZXR10_MOT_TSEC_ATTR_BDLWT_NA       0x0#define ZXR10_MOT_TSEC_ATTR_BDLWT_L2       0x2#define ZXR10_MOT_TSEC_ATTR_BDLWT_L2_LOCK  0x3#define ZXR10_MOT_TSEC_ATTR_BDLWT(v)       ((v&0x00000003)<<10)#define ZXR10_MOT_TSEC_ATTR_RDSEN          0x00000080#define ZXR10_MOT_TSEC_ATTR_RBDSEN         0x00000040#define ZXR10_MOT_TSEC_ATTRELI_EL(v)       ((v&0x00003fff)<<16)#define ZXR10_MOT_TSEC_ATTRELI_EI(v)       (v&0x00003fff)/* TSEC init string parameters *//* "MMBASE:TSEC_PORT:MAC_ADRS:PHY_DEF_MODES:USER_FLAGS:FUNC_TABLE:EXT_PARMS"  *//*        MMBASE - 85xx local base address. Used as base for driver memory space. *      MAC_ADRS - Mac address in 12 digit format eg. 00-A0-1E-11-22-33 *  PHY_DEF_MODE - Default Attributes passed to the MII driver. * USER_DEF_MODE - Mandatory initialization user parameters. *    FUNC_TABLE - Table of BSP and Driver callbacks *         PARMS - Address of a structure that contains required initialization *                 parameters and driver specific tuning parameters. *     EXT_PARMS - Address of a structure that contains optional initialization *                 parameters and driver specific tuning parameters. *//* MII/PHY PHY_DEF_MODE flags to init the phy driver */#define ZXR10_MOT_TSEC_USR_MODE_DEFAULT         0#define ZXR10_MOT_TSEC_USR_PHY_NO_AN   0x00000001  /* do not auto-negotiate */#define ZXR10_MOT_TSEC_USR_PHY_TBL     0x00000002  /* use negotiation table */#define ZXR10_MOT_TSEC_USR_PHY_NO_FD   0x00000004  /* do not use full duplex */#define ZXR10_MOT_TSEC_USR_PHY_NO_100  0x00000008  /* do not use 100Mbit speed */#define ZXR10_MOT_TSEC_USR_PHY_NO_HD   0x00000010  /* do not use half duplex */#define ZXR10_MOT_TSEC_USR_PHY_NO_10   0x00000020  /* do not use 10Mbit speed */#define ZXR10_MOT_TSEC_USR_PHY_MON     0x00000040  /* use PHY Monitor */#define ZXR10_MOT_TSEC_USR_PHY_ISO     0x00000080  /* isolate a PHY *//* ECNTRL Ethernet Control */#define ZXR10_MOT_TSEC_USR_STAT_CLEAR     0x00000100 /* init + runtime clear mstats*/#define ZXR10_MOT_TSEC_USR_STAT_AUTOZ     0x00000200 /* init */#define ZXR10_MOT_TSEC_USR_STAT_ENABLE    0x00000400 /* init *//* PHY bus configuration selections */#define ZXR10_MOT_TSEC_USR_MODE_MASK      0x0003f800#define ZXR10_MOT_TSEC_USR_MODE_TBI       0x00000800#define ZXR10_MOT_TSEC_USR_MODE_RTBI      0x00001000#define ZXR10_MOT_TSEC_USR_MODE_MII       0x00002000#define ZXR10_MOT_TSEC_USR_MODE_GMII      0x00004000#define ZXR10_MOT_TSEC_USR_MODE_RGMII     0x00008000#define ZXR10_MOT_TSEC_USR_MODE_RGMII_10  0x00010000#define ZXR10_MOT_TSEC_USR_MODE_RGMII_100 0x00020000/* TSEC extended initialization parameters *//* Bit flags *//* DMACTRL - Configure the DMA block */#define ZXR10_MOT_TSEC_TX_SNOOP_EN          0x00000001 /* snoop Tx Clusters */#define ZXR10_MOT_TSEC_TX_BD_SNOOP_EN       0x00000002 /* snoop txbds */#define ZXR10_MOT_TSEC_TX_WWR               0x00000004 /* init */#define ZXR10_MOT_TSEC_TXBD_WOP             0x00000008 /* init *//* RCTRL - Receive Control flags */#define ZXR10_MOT_TSEC_BROADCAST_REJECT     0x00000010 /* Broadcast Reject */#define ZXR10_MOT_TSEC_PROMISCUOUS_MODE     0x00000008 /* Promiscuous Mode*/#define ZXR10_MOT_TSEC_RX_SHORT_FRAME       0x00000004 /* Rx Shorter Frames */                                                 /* if (frame<MINFLR)*//* MACCFG1 - Mac Configuration */#define ZXR10_MOT_TSEC_MAC_LOOPBACK         0x00000080  /* init + runtime */#define ZXR10_MOT_TSEC_MAC_RX_FLOW          0x00000100  /* enable Rx Flow */#define ZXR10_MOT_TSEC_MAC_TX_FLOW          0x00000200  /* enable Tx Flow *//* MACCFG2 Mac Configuration */#define ZXR10_MOT_TSEC_MAC_HUGE_FRAME       0x00000400  /* enable huge frame support*/#define ZXR10_MOT_TSEC_MAC_PADCRC           0x00000800  /* MAC pads short frames */                                                  /* and appends CRC */#define ZXR10_MOT_TSEC_MAC_CRC_ENABLE       0x00001000  /* MAC appends CRC */#define ZXR10_MOT_TSEC_MAC_DUPLEX           0x00002000  /* MAC duplex mode *//* ATTR */#define ZXR10_MOT_TSEC_RX_SNOOP_ENABLE      0x00004000  /* snoop Rx cluster */#define ZXR10_MOT_TSEC_RXBD_SNOOP_ENABLE    0x00008000  /* snoop rxbds *//* MII flags */#define ZXR10_MOT_TSEC_MII_NOPRE            0x00010000  /* suppress preamble */#define ZXR10_MOT_TSEC_MII_RESET            0x00020000  /* runtime reset MII MGMT */#define ZXR10_MOT_TSEC_MII_SCAN_CYCLE       0x00040000  /* Continuous read */#define ZXR10_MOT_TSEC_MII_READ_CYCLE       0x00080000  /* Preform single read *//* HALDUP */#define ZXR10_MOT_TSEC_HALDUP_ALTBEB        0x00100000  /* use alternate backoff */                                                  /* algorithm */#define ZXR10_MOT_TSEC_HALDUP_BACK_PRESSURE 0x00200000  /* immediate retrans back */                                                  /* pressure */#define ZXR10_MOT_TSEC_HALDUP_EX_DEFERENCE  0x00400000#define ZXR10_MOT_TSEC_HALDUP_NOBACKOFF     0x00800000/* Driver Runtime Attributes */#define ZXR10_MOT_TSEC_POLLING_MODE         0x01000000    /* polling mode */#define ZXR10_MOT_TSEC_MULTICAST_MODE       0x02000000    /* multicast addressing *//* TSEC Attribute Default Values */#define ZXR10_MOT_TSEC_IMASK_DEFAULT (ZXR10_MOT_TSEC_IEVENT_RXC  | ZXR10_MOT_TSEC_IEVENT_TXC   | \                                ZXR10_MOT_TSEC_IEVENT_MSRO | ZXR10_MOT_TSEC_IEVENT_GTSC  | \                                ZXR10_MOT_TSEC_IEVENT_TXB  | ZXR10_MOT_TSEC_IEVENT_RXB0  | \                                ZXR10_MOT_TSEC_IEVENT_TXF  | ZXR10_MOT_TSEC_IEVENT_GRSC  | \                                ZXR10_MOT_TSEC_IEVENT_RXF0 )#define ZXR10_MOT_TSEC_IEVENT_ERROR  (ZXR10_MOT_TSEC_IEVENT_BSY  | ZXR10_MOT_TSEC_IEVENT_EBERR | \                                ZXR10_MOT_TSEC_IEVENT_TXE  | ZXR10_MOT_TSEC_IEVENT_LC    | \                                ZXR10_MOT_TSEC_IEVENT_CRL  | ZXR10_MOT_TSEC_IEVENT_XFUN  | \                                ZXR10_MOT_TSEC_IEVENT_BABT | ZXR10_MOT_TSEC_IEVENT_BABR )#define ZXR10_MOT_TSEC_MACCFG1_DEFAULT (0x0)/* IF_MODE = 1 ; MII mode 10/100 only */#define ZXR10_MOT_TSEC_MACCFG2_DEFAULT  \                (ZXR10_MOT_TSEC_MACCFG2_PRE_LEN(7)  | \                 ZXR10_MOT_TSEC_MACCFG2_FULL_DUPLEX | \