/* Plx9054.h: Plx9054 PCI橋片驅(qū)動頭文件*/
/* author: Wang.qi Jilin Univ. */

/*
modification history
------------------
2006-09-17
*/

#ifndef	INCplx9054h
#define	INCplx9054h

#ifdef __cplusplus
extern "C" {
#endif

/* includes (header file) 頭包含文件 */

/* define 宏定義 */
/*#define  PLX_DEBUG*/                /* 沒有連接實(shí)際設(shè)備時(shí)做單元測試的開關(guān)*/
#define  PLX_DEBUG_PRINT    /* 打印調(diào)試信息開關(guān)*/
#define  PLX_INPUT_CHECK
#define  PLX_9054_VENDORID     0x10B5
#if 0
#define  PLX_9054_DEVICEID      0x5406
#else
#define  PLX_9054_DEVICEID      0x9054
#endif
#define EXT_INTERRUPT_BASE      INT_NUM_IRQ0    /* irq0     */
#define PCI_DEV_MMU_MSK           (~(VM_PAGE_SIZE - 1))   /* Mask MMU page */
#define PCI_DEV_ADRS_SIZE         VM_PAGE_SIZE    /* one page */

#define PLX9054_DMA_TIME_OUT  120    /*DMA 操作超時(shí)時(shí)間2秒*/    

/*
 * default values if PCI_CFG_TYPE defined to be PCI_CFG_FORCE
 * 因BIOS已經(jīng)自動對PCI設(shè)備做了資源分配，所以PCI_CFG_TYPE == PCI_CFG_SPEC
 * note: memory addresses must be aligned on MMU page boundaries
 */
#define PLX9054_IO_ADR0   	0xf400
#define PLX9054_MEM_ADR0  	0xfd000000
#define PLX9054_INT_LVL0  	0x0b
#define PLX9054_INT_VEC0  	0

#define PLX9054_IO_ADR1   	0xf420
#define PLX9054_MEM_ADR1  	0xfd200000
#define PLX9054_INT_LVL1  	0x05
#define PLX9054_INT_VEC1  	0

#define PLX9054_IO_ADR2   	0xf440
#define PLX9054_MEM_ADR2  	0xfd300000
#define PLX9054_INT_LVL2  	0x0c
#define PLX9054_INT_VEC2  	0

#define PLX9054_IO_ADR3   	0xf460
#define PLX9054_MEM_ADR3  	0xfd400000
#define PLX9054_INT_LVL3  	0x9
#define PLX9054_INT_VEC3  	0

#define  PLX9054_MAX_DEV         4               /*最大支持4塊PLX9054擴(kuò)展卡*/

 /******* Interrupt identifiers **************/
#define INTR_TYPE_NONE                      0           
#define INTR_TYPE_LOCAL_1                 (1 << 0)
#define INTR_TYPE_LOCAL_2                 (1 << 1)
#define INTR_TYPE_PCI_ABORT             (1 << 2)
#define INTR_TYPE_DOORBELL               (1 << 3)
#define INTR_TYPE_OUTBOUND_POST    (1 << 4)
#define INTR_TYPE_DMA_0                     (1 << 5)
#define INTR_TYPE_DMA_1                     (1 << 6)
#define INTR_TYPE_DMA_2                     (1 << 7)
#define INTR_TYPE_DMA_3                     (1 << 8)
#define INTR_TYPE_SOFTWARE               (1 << 9)

enum 
{
    BIT0  = 0x00000001,
    BIT1  = 0x00000002,
    BIT2  = 0x00000004,
    BIT3  = 0x00000008,
    BIT4  = 0x00000010,
    BIT5  = 0x00000020,
    BIT6  = 0x00000040,
    BIT7  = 0x00000080,
    BIT8  = 0x00000100,
    BIT9  = 0x00000200,
    BIT10 = 0x00000400,
    BIT11 = 0x00000800,
    BIT12 = 0x00001000,
    BIT13 = 0x00002000,
    BIT14 = 0x00004000,
    BIT15 = 0x00008000,
    BIT16 = 0x00010000,
    BIT17 = 0x00020000,
    BIT18 = 0x00040000,
    BIT19 = 0x00080000,
    BIT20 = 0x00100000,
    BIT21 = 0x00200000,
    BIT22 = 0x00400000,
    BIT23 = 0x00800000,
    BIT24 = 0x01000000,
    BIT25 = 0x02000000,
    BIT26 = 0x04000000,
    BIT27 = 0x08000000,
    BIT28 = 0x10000000,
    BIT29 = 0x20000000,
    BIT30 = 0x40000000,
    BIT31 = 0x80000000
};


/* registers */
/* PCI Configuaration register definitions  */
enum {
    PCI_IDR  = 0x00,
    PCI_CR   = 0x04,
    PCI_SR   = 0x06,
    PCI_REV  = 0x08,
    PCI_CCR  = 0x09,
    PCI_LSR  = 0x0c,
    PCI_LTR  = 0x0d,
    PCI_HTR  = 0x0e,
    PCI_BISTR= 0x0f,
    PCI_BAR0 = 0x10,
    PCI_BAR1 = 0x14,
    PCI_BAR2 = 0x18,
    PCI_BAR3 = 0x1c,
    PCI_BAR4 = 0x20,
    PCI_BAR5 = 0x24,
    PCI_CIS  = 0x28,
    PCI_SVID = 0x2c,
    PCI_SID  = 0x2e,
    PCI_ERBAR= 0x30,
    PCI_ILR  = 0x3c,
    PCI_IPR  = 0x3d,
    PCI_MGR  = 0x3e,
    PCI_MLR  = 0x3f
};

enum {
    AD_PCI_BAR0 = 0,
    AD_PCI_BAR1 = 1,
    AD_PCI_BAR2 = 2,
    AD_PCI_BAR3 = 3,
    AD_PCI_BAR4 = 4,
    AD_PCI_BAR5 = 5,
    AD_PCI_BAR_EPROM = 6,
    AD_PCI_BARS = 7,
};

/* PLX register definitions */
enum {
    P9054_LAS0RR    = 0x00,
    P9054_LAS0BA    = 0x04,
    P9054_MARBR     = 0x08,
    P9054_BIGEND    = 0x0c,
    P9054_LMISC     = 0x0d,
    P9054_PROT_AREA = 0x0e,
    P9054_EROMRR    = 0x10,
    P9054_EROMBA    = 0x14,
    P9054_LBRD0     = 0x18,
    P9054_DMRR      = 0x1c,
    P9054_DMLBAM    = 0x20,
    P9054_DMLBAI    = 0x24,
    P9054_DMPBAM    = 0x28,
    P9054_DMCFGA    = 0x2c,
    P9054_OPQIS     = 0x30,
    P9054_OPQIM     = 0x34,
    P9054_IQP       = 0x40,
    P9054_OQP       = 0x44,
    P9054_MQCR      = 0xc0,
    P9054_QBAR      = 0xc4,
    P9054_MBOX0_OLD = 0x40,
    P9054_MBOX1_OLD = 0x44,
    P9054_MBOX0     = 0x78,
    P9054_MBOX1     = 0x7c,
    P9054_MBOX2     = 0x48,
    P9054_MBOX3     = 0x4c,
    P9054_MBOX4     = 0x50,
    P9054_MBOX5     = 0x54,
    P9054_MBOX6     = 0x58,
    P9054_MBOX7     = 0x5c,
    P9054_P2LDBELL  = 0x60,
    P9054_L2PDBELL  = 0x64,
    P9054_INTCSR    = 0x68,
    P9054_CNTRL     = 0x6c,
    P9054_PCIHIDR   = 0x70,
    P9054_PCIHREV   = 0x74,
    P9054_DMAMODE   = 0x80,
    P9054_DMAPADR   = 0x84,
    P9054_DMALADR   = 0x88,
    P9054_DMASIZ    = 0x8c,
    P9054_DMADPR    = 0x90,
    P9054_DMAMODE1  = 0x94,
    P9054_DMAPADR1  = 0x98,
    P9054_DMALADR1  = 0x9c,
    P9054_DMASIZ1   = 0xa0,
    P9054_DMADPR1   = 0xa4,
    P9054_DMACSR    = 0xa8,
    P9054_DMACSR1   = 0xa9,
    P9054_DMAARB    = 0xac,
    P9054_DMATHR    = 0xb0,
    P9054_DMADAC0   = 0xb4,
    P9054_DMADAC1   = 0xb8,
    P9054_IFHPR     = 0xc8,
    P9054_IFTPR     = 0xcc,
    P9054_IPHPR     = 0xd0,
    P9054_IPTPR     = 0xd4,
    P9054_OFHPR     = 0xd8,
    P9054_OFTPR     = 0xdc,
    P9054_OPHPR     = 0xe0,
    P9054_OPTPR     = 0xe4,
    P9054_QSR       = 0xe8,
    P9054_LAS1RR    = 0xf0,
    P9054_LAS1BA    = 0xf4,
    P9054_LBRD1     = 0xf8,
    P9054_DMDAC     = 0xfc
};

/* PLX specific PCI configuration registers*/
enum {
    P9054_VPD_ADDR   = 0x4E,
    P9054_VPD_DATA   = 0x50,
};

typedef enum