/********************************************************************/
/*  Copyright 2004 by SEED Incorporated.							*/
/*  All rights reserved. Property of SEED Incorporated.				*/
/*  Restricted rights to use, duplicate or disclose this code are	*/
/*  granted through contract.									    */
/*  															    */
/********************************************************************/
#include <csl.h>
#include <std.h>
#include <csl_emifa.h>
#include <csl_i2c.h>
#include <csl_gpio.h>
#include <csl_irq.h>
#include <csl_chip.h>
#include "iic.h"
#include "seeddm642_aic23.h"

/*SEEDDM642的emifa的設(shè)置結(jié)構(gòu)*/
EMIFA_Config Seeddm642ConfigA ={
	   0x00052078,/*gblctl EMIFA(B)global control register value */
	   			  /*將CLK6、4、1使能；將MRMODE置1；使能EK2EN,EK2RATE*/
	   0xffffffd3,/*cectl0 CE0 space control register value*/
	   			  /*將CE0空間設(shè)為SDRAM*/
	   0x73a28e01,/*cectl1 CE1 space control register value*/
	   			  /*Read hold: 1 clock;
	   			    MTYPE : 0000,選擇8位的異步接口
	   			    Read strobe ：001110；14個clock寬度
	   			    TA：2 clock; Read setup 2 clock;
	   			    Write hold :2 clock; Write strobe: 14 clock
	   			    Write setup :7 clock
	   			    --					 ---------------
	   			  	  \		 14c		/1c
	   			 	   \----------------/ */
	   0x22a28a22, /*cectl2 CE2 space control register value*/
       0x22a28a42, /*cectl3 CE3 space control register value*/
	   0x57115000, /*sdctl SDRAM control register value*/
	   0x0000081b, /*sdtim SDRAM timing register value*/
	   0x001faf4d, /*sdext SDRAM extension register value*/
	   0x00000002, /*cesec0 CE0 space secondary control register value*/
	   0x00000002, /*cesec1 CE1 space secondary control register value*/
	   0x00000002, /*cesec2 CE2 space secondary control register value*/
	   0x00000073 /*cesec3 CE3 space secondary control register value*/	
};

/*SEEDDM642的IIC的設(shè)置結(jié)構(gòu)*/
I2C_Config SEEDDM642IIC_Config = {
    0,  /* master mode,  i2coar;采用主模式   */
    0,  /* no interrupt, i2cimr;只寫，不讀，采用無中斷方式*/
    (20-5), /* scl low time, i2cclkl;  */
    (20-5), /* scl high time,i2cclkh;  */
    1,  /* configure later, i2ccnt;*/
    0,  /* configure later, i2csar;*/
    0x4ea0, /* master tx mode,     */
            /* i2c runs free,      */
            /* 8-bit data + NACK   */
            /* no repeat mode      */
    (75-1), /* 4MHz clock, i2cpsc  */
};

CHIP_Config SEEDDM642percfg = {
	CHIP_VP2+\
	CHIP_VP1+\
	CHIP_VP0+\
	CHIP_I2C+\
	CHIP_MCASP0
};

I2C_Handle hSeeddm642i2c;
/*設(shè)置需打開的音頻的句柄*/
SEEDDM642_AIC23_Handle dm642aic23handle0,dm642aic23handle1;
SEEDDM642_AIC23_Handle dm642aic23handle2,dm642aic23handle3;
/* Internal codec state used to simulate read/write functionality */
SEEDDM642_AIC23_Config codecstate = SEEDDM642_AIC23_DEFAULTCONFIG;
MCASP_Handle SEEDdm642codec;
extern far void vectors();

/*此程序可將四個采集口的數(shù)據(jù)經(jīng)過Video Port0送出*/
void main()
{
	Uint32 codecdata[4];
/*-------------------------------------------------------*/
/* perform all initializations                           */
/*-------------------------------------------------------*/
	/*Initialise CSL，初始化CSL庫*/
	CSL_init();
	CHIP_config(&SEEDDM642percfg);
/*----------------------------------------------------------*/
	/*EMIFA的初始化，將CE0設(shè)為SDRAM空間，CE1設(shè)為異步空間
	 注，DM642支持的是EMIFA，而非EMIF*/
	EMIFA_config(&Seeddm642ConfigA);
/*----------------------------------------------------------*/
	/*中斷向量表的初始化*/
	//Point to the IRQ vector table
    IRQ_setVecs(vectors);
    IRQ_nmiEnable();
    IRQ_globalEnable();
    IRQ_map(IRQ_EVT_VINT1, 11);
    IRQ_map(IRQ_EVT_VINT0, 12);
    IRQ_reset(IRQ_EVT_VINT1);
    IRQ_reset(IRQ_EVT_VINT1);	
/*----------------------------------------------------------*/	
	/*AIC23B的初始化*/
	hSeeddm642i2c = I2C_open(I2C_PORT0,I2C_OPEN_RESET);
	I2C_config(hSeeddm642i2c,&SEEDDM642IIC_Config);
	/*配置第一路到第四路音頻輸入*/
	/*第一通路AIC23工作在主模式*/
//	codecstate.regs[SEEDDM642_AIC23_DIGIF] = 0x13;
	dm642aic23handle0 = EVMDM642_AIC23_open(hSeeddm642i2c,0,&codecstate);
	/*其它三路工作在從模式*/
	codecstate.regs[SEEDDM642_AIC23_DIGIF] = 0x13;
	dm642aic23handle1 = EVMDM642_AIC23_open(hSeeddm642i2c,1,&codecstate);
	dm642aic23handle2 = EVMDM642_AIC23_open(hSeeddm642i2c,2,&codecstate);
	dm642aic23handle3 = EVMDM642_AIC23_open(hSeeddm642i2c,3,&codecstate);		
/*----------------------------------------------------------*/
	/*MCASP的初始化*/
	SEEDdm642codec = SEEDDM642_AIC23_openCodec();
/*----------------------------------------------------------*/
	/*音頻的采集與回放*/
	for(;;)
	{
		if(MCASP_FGETH(SEEDdm642codec,RSTAT,RDATA))
		{
			codecdata[0] = MCASP_RGETH(SEEDdm642codec,RBUF1);

			MCASP_RSETH(SEEDdm642codec,XBUF0,codecdata[0]);
			
			codecdata[1] = MCASP_RGETH(SEEDdm642codec,RBUF3);
			MCASP_RSETH(SEEDdm642codec,XBUF2,codecdata[1]);
			
			codecdata[2] = MCASP_RGETH(SEEDdm642codec,RBUF5);			MCASP_RSETH(SEEDdm642codec,XBUF4,codecdata[2]);	
			
			codecdata[3] = MCASP_RGETH(SEEDdm642codec,RBUF7);
			MCASP_RSETH(SEEDdm642codec,XBUF6,codecdata[3]);			
		
		}
		else
		{
			    asm(" nop");
		}
	}
}