} Audio_States;


//-----------------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------------


unsigned char code RegValue[] = {
//      CLOCK_A, (this register is configured separately inside CC1100_Init() )
//      0x25,

//    CLOCK_B,
      0x25,

//    VCO,
      0x44,

//    MODEM,
      0x50,

//    DEVIATION,
      0x5A,

//    AFC_CONTROL,
      0xCC,

//    FILTER,
      0x80,

//    VGA1,
      0x65,

//    VGA2,
      0x57,

//    VGA3,
      0x34,

//    VGA4,
      0x3E,

//    LOCK,
      0x20,

//    FRONTEND,
      0x76,

//    ANALOG,
      0x86,

//    BUFF_SWING,
      0x50,

//    BUFF_CURRENT,
      0x25,

//    PLL_BW,
      0xAE,

//    CALIBRATE,
      0x35,

//    PA_POWER,
      0xFF,

//    MATCH,
      0x22,

//    PHASE_COMP,
      0x00,

//    GAIN_COMP,
      0x00,

//    POWERDOWN,
      0x00,

//    TEST1,
      0x4D,

//    TEST2,
      0x10,

//    TEST3,
      0x06,

//    TEST4,
      0x00,

//    TEST5,
      0x40,

//    TEST6,
      0x00,

//    TEST7,
      0x00

};


// 1/2 Period Sine Wave Table
static char code Audio_SineTable[16] = {
   0x00,0x18,0x30,0x47,0x5a,0x6a,0x76,0x7d,
   0x7f,0x7d,0x76,0x6a,0x5a,0x47,0x30,0x18
};



// the mapping from DPCM quantization values to dpcm codes (array index)
short code Q_VALUES[16] = {0,
                     -high_high,
                     -high_mid,
                     -high_low,
                     -middle,
                     -low_high,
                     -low_mid,
                     -low_low,
                     0,
                     low_low,
                     low_mid,
                     low_high,
                     middle,
                     high_low,
                     high_mid,
                     high_high};

// CC1100 Interface Bits
sbit PALE = P0^2;
sbit DIO = P1^2;
sbit DCLK = P1^0;
sbit PCLK = P0^3;
sbit PDI = P0^6;
sbit PDO = P0^7;

// AN147 PCB Pins
sbit DEBUG= P1^4;
sbit LED1 = P1^5;
sbit LED2 = P1^6;
sbit SW2  = P1^7;


// RX/TX State Machine variables, flags
RXTX_StateMachineStates RXTX_StateMachine;
void CLEAR_FIFOS(void);                // resets all FIFOs to default values

bit RXTX_ResetVariables;               // indicates to RF state machines that
                                       // variables should be re-initialized

unsigned char RXTX_MasterSelect;       // determines whether RF state machine
                                       // behaves as slave or master across
                                       // the RF link

bit RXTX_RunInitSlave;                 // signals RF state machine to run
                                       // as slave

bit SPI_TimeOutEvent;                  // set when SPI_Timer reaches its
                                       // terminal value

unsigned int SPI_Timer;                // time base for RF state machine

unsigned char SPI_DataBytes;           // counts number of data bytes
                                       // transmitted or received during
                                       // current packet time

int DAC_Error;                         // used to measure how far buffers are
                                       // from defined ideal value

unsigned char RXTX_NoPreambleCount;    // counts number of consecutive packet
                                       // receptions that have failed due to
                                       // finding no preamble bytes

bit SPI_TimerEnable;                   // signals that SPI_Timer should
                                       // be incremented

TimeOut_EntryModes TimeOut_EntryMode;  // indicates whether packet
                                       // reception/transmission was successful
                                       // or unsuccessful

Audio_States Audio_LocalState;         // shows whether audio signal is
Audio_States Audio_RemoteState;        // "quiet" or "loud"

bit RXTX_Indicator;                    // shows whether RF state machine is in
                                       // transmit or receive mode

bit OutputByteReady;                   // toggles to indicate whether both
                                       // nibbles of OutputByte inside
                                       // DPCM_Compress contain valid compressed
                                       // data

// TransmitFIFO Variables
unsigned char TransmitFIFO_COUNT;
bit TransmitFIFO_EMPTY;
bit TransmitFIFO_OF;
bit TransmitFIFO_UF;
bit TransmitFIFO_FULL;
bit CC1100_StartUpCall;
unsigned char idata TransmitFIFO_FIRST;
unsigned char idata TransmitFIFO_LAST;
unsigned char xdata TransmitFIFO_FIFO[TransmitFIFO_FIFOSIZE];


// ReceiveFIFO Variables
unsigned char ReceiveFIFO_COUNT;
bit ReceiveFIFO_EMPTY;
bit ReceiveFIFO_OF;
bit ReceiveFIFO_UF;
bit ReceiveFIFO_FULL;
unsigned char idata ReceiveFIFO_FIRST;
unsigned char idata ReceiveFIFO_LAST;
unsigned char xdata ReceiveFIFO_FIFO[ReceiveFIFO_FIFOSIZE];



// ADCRXFIFO Variables
unsigned char ADCRXFIFO_COUNT;
bit ADCRXFIFO_EMPTY;
bit ADCRXFIFO_OF;
bit ADCRXFIFO_UF;
bit ADCRXFIFO_FULL;
unsigned char idata ADCRXFIFO_FIRST;
unsigned char idata ADCRXFIFO_LAST;
int xdata ADCRXFIFO_FIFO[ADCRXFIFO_FIFOSIZE];


// DACTXFIFO Variables
unsigned char DACTXFIFO_COUNT;
bit DACTXFIFO_EMPTY;
bit DACTXFIFO_OF;
bit DACTXFIFO_UF;
bit DACTXFIFO_FULL;
bit DACTXFIFO_DECOMPRESS_HALT;
unsigned char idata DACTXFIFO_FIRST;
unsigned char idata DACTXFIFO_LAST;
unsigned int xdata DACTXFIFO_FIFO[DACTXFIFO_FIFOSIZE];



//-----------------------------------------------------------------------------
// Macros
//-----------------------------------------------------------------------------

// configures Cross Bar to route SPI to port pins
#define RouteSPI() P1SKIP &= ~0x07;  P1MDOUT |= 0x10;  XBR1 = 0x41;  XBR0 = 0x02

// configures Cross Bar to route PCA0 module 0 to port pins
#define RoutePCA() P1SKIP &= ~0x07;  P1MDOUT &=~0x10;  P1SKIP |=  0x03;  XBR0 = 0x00;  XBR1 = 0x41

// used in RF state machine to determine SPI_Timer timing thresholds
#define SPI_ms(x) (x * SPI_DATARATE / 8) / 1000
#define SPI_us(x) ((x * SPI_DATARATE / 8) / 1000) / 1000

#define SPI_SlopTimeOut SPI_ms(1) + SPI_us(500)

#define SPI_CalibrationWaitTime SPI_ms(1)

#define SPI_PacketTime SPI_ms(17)

#define SPI_TX()  P1MDIN |=  0x02; P1MDOUT |=  0x02
#define SPI_RX()  P1MDIN &= ~0x02; P1MDOUT &= ~0x02

//-----------------------------------------------------------------------------
// MAIN Routine
//-----------------------------------------------------------------------------
void main (void) {

   PCA0MD &= ~0x40;                    // disable watchdog timer

   PORT_Init();                        // initialize and enable the Crossbar
   SYSCLK_Init();                      // initialize oscillator
   Timer2_Init(SYSCLK/SAMPLE_RATE);    // initialize timer to overflow
                                       // at SAMPLE_RATE

   ADC0_Init();                        // ADC samples on Timer 2 interrupts
   SPI_Init();                         // init
   Timer3_Init(SYSCLK/DAC_UPDATERATE); // initialize timer 3 to overflow at
                                       // DACUPDATERATE
   PCA0_Init();                        // initialize PCA0 module 0 for
                                       // edge-triggered interrupts
   IDAC0_Init();                       // enable DAC outputs at P0.1

   Variables_Init();

   WaitMS_360(500);


   CC1100_StartUpCall = TRUE;          // forces CC1100_Init to turn on all
                                       // RF transceiver components

   while(!CC1100_Init()){}             // initalize the RF transceiver

   CC1100_StartUpCall = FALSE;

   WaitMS_360(200);

   RXTX_InitSlave();                   // configure RF state machine to slave
                                       // mode, where it will search for a
                                       // Communication Channel


   AD0EN = 1;                          // enables ADC0
   EA = 1;                             // enables all interrupts

   while (1)
   {

      FIFO_ManagementRoutine();        // compresses and decompresses
                                       // audio samples

      // if audile signal present is present at the audio input and the
      // system is not already communicating across the RF line,
      // then initiate a Communication Channel
      if((Audio_LocalState == Audio_Loud) &&
         (RXTX_MasterSelect == RXTX_Searching) &&
         (RXTX_RunInitSlave != TRUE))
      {
         EA = 0;                       // disable interrupts
         RXTX_InitMaster();            // configure to be master endpoint
         EA = 1;                       // re-enable interrupts
      }


      if(Audio_LocalState == Audio_Loud) LED1 = 0; else LED1 = 1;


      // only run the following conditional if SPIBSY == 0, that is
      // if the Audio_ShutdownChannel Audio_Level command has been transmitted
      // so that the receiving slave will no to end transmission
      if((RXTX_RunInitSlave == TRUE) && !(SPI0CFG & 0x80))
      {
         EA = 0;                       // disable interrupts
         RXTX_InitSlave();             // configure to be slave endpoint
                                       // and search for a transmitting master
         EA = 1;                       // re-enable interrupts
      }

  } // end while(1)

} // end void main()


//-----------------------------------------------------------------------------
// Initialization Functions
//-----------------------------------------------------------------------------
//

//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use the internal 24.5MHz
// oscillator as its clock source.  Also enables missing clock detector
// reset and enables the VDD monitor as a reset source.
//
void SYSCLK_Init (void)
{
   OSCICN |= 0x03;                     // set clock to 24.5 MHz
   RSTSRC  = 0x06;                     // enable missing clock detector
}

//-----------------------------------------------------------------------------
// ADC0_Init
//-----------------------------------------------------------------------------
//
// Configure ADC0 to use Timer2 overflows as conversion source, and to
// generate an interrupt on conversion complete.
// Enables ADC end of conversion interrupt. Leaves ADC disabled.
//
void ADC0_Init(void)
{
   REF0CN = 0x03;                      // set VREF pin as voltage reference,
                                       // enable internal bias generator and
                                       // internal reference buffer

   ADC0CN = 0x02;                      // overflow on Timer 2 starts
                                       // conversion
                                       // ADC0 disabled and in normal
                                       // tracking mode
   AMX0P  = 0x0B;                      // select P1.3 as positive conv. source
   AMX0N  = 0x11;                      // set ADC to single-ended mode
   ADC0CF = (SYSCLK/3000000) << 3;     // ADC Conversion clock = 3 MHz
   ADC0CF&= ~0x04;                     // ADC readings are right-justified
   EIE1  |= 0x08;                      // enable ADC0 EOC interrupt
}

//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
//
// P0.0 - VREF
// P0.1 - IDAC0 Output
// P0.2 - PSEL
// P0.3 - PCLK
// P0.4 -
// P0.5 -
// P0.6 - PDI
// P0.7 - PDO
// P1.0 - SCK (DCLK)
// P1.1 - MISO (DIO)
// P1.2 - MOSI (DIO)