#define I2C_TRISER_TRISE ((u8)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */

#ifdef HW_PLATFORM_TEST_CHIP
#define I2C_PECR_PEC ((u8)0xFF) /*!< */ /* TBD not in datasheet */
#endif

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Interrupt Controller (ITC)
  */
typedef volatile struct ITC_struct
{
  u8 ISPR0; /* Interrupt Software Priority register 0 */
  u8 ISPR1; /* Interrupt Software Priority register 1 */
  u8 ISPR2; /* Interrupt Software Priority register 2 */
  u8 ISPR3; /* Interrupt Software Priority register 3 */
  u8 ISPR4; /* Interrupt Software Priority register 4 */
  u8 ISPR5; /* Interrupt Software Priority register 5 */
  u8 ISPR6; /* Interrupt Software Priority register 6 */
  u8 ISPR7; /* Interrupt Software Priority register 7 */
}
ITC_TypeDef;

/** @addtogroup ITC_Registers_Reset_Value
  * @{
  */
#define ITC_SPRX_RESET_VALUE ((u8)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief External Interrupt Controller (EXTI)
  */
typedef volatile struct EXTI_struct
{
  u8 CR1; /* External Interrupt Control Register for PORTA to PORTD */
  u8 CR2; /* External Interrupt Control Register for PORTE and TLI */
}
EXTI_TypeDef;

/** @addtogroup EXTI_Registers_Reset_Value
  * @{
  */

#define EXTI_CR1_RESET_VALUE ((u8)0x00)
#define EXTI_CR2_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup EXTI_Registers_Bits_Definition
  * @{
  */

#define EXTI_CR1_PDIS ((u8)0xC0) /*!< EXTI PORTD external interrupt sensitivity bit Mask */
#define EXTI_CR1_PCIS ((u8)0x30) /*!< EXTI PORTC external interrupt sensitivity bit Mask */
#define EXTI_CR1_PBIS ((u8)0x0C) /*!< EXTI PORTB external interrupt sensitivity bit Mask */
#define EXTI_CR1_PAIS ((u8)0x03) /*!< EXTI PORTA external interrupt sensitivity bit Mask */

#define EXTI_CR2_TLIE ((u8)0x04) /*!< EXTI TLI   external interrupt sensitivity bit Mask */
#define EXTI_CR2_PEIS ((u8)0x03) /*!< EXTI PORTE external interrupt sensitivity bit Mask */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief General Purpose I/Os (GPIO)
  */
typedef volatile struct GPIO_struct
{
  u8 ODR; /*!< Output Data Register */
  u8 IDR; /*!< Input Data Register */
  u8 DDR; /*!< Data Direction Register */
  u8 CR1; /*!< Configuration Register 1 */
  u8 CR2; /*!< Configuration Register 2 */
}
GPIO_TypeDef;

/** @addtogroup GPIO_Registers_Reset_Value
  * @{
  */
#define GPIO_ODR_RESET_VALUE ((u8)0x00)
#define GPIO_DDR_RESET_VALUE ((u8)0x00)
#define GPIO_CR1_RESET_VALUE ((u8)0x00)
#define GPIO_CR2_RESET_VALUE ((u8)0x00)
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief FLASH and Data EEPROM
  */
typedef volatile struct FLASH_struct
{
  u8 CR1;       /*!< Flash control register 1 */
  u8 CR2;       /*!< Flash control register 2 */
  u8 NCR2;      /*!< Flash complementary control register 2 */
  u8 FPR;       /*!< Flash protection register */
  u8 NFPR;      /*!< Flash complementary protection register */
  u8 IAPSR;     /*!< Flash in-application programming status register */
  u8 RESERVED1;
  u8 RESERVED2;
  u8 PUNPR;     /*!< Flash program memory unprotection register */
  u8 RESERVED3;
  u8 DUNPR;     /*!< Data EEPROM unprotection register */
}
FLASH_TypeDef;

/** @addtogroup FLASH_Registers_Reset_Value
  * @{
  */
#define FLASH_CR1_RESET_VALUE   ((u8)0x00)
#define FLASH_CR2_RESET_VALUE   ((u8)0x00)
#define FLASH_NCR2_RESET_VALUE  ((u8)0xFF)
#define FLASH_IAPSR_RESET_VALUE ((u8)0x00)
#define FLASH_PUNPR_RESET_VALUE ((u8)0x00)
#define FLASH_DUNPR_RESET_VALUE ((u8)0x00)
/**
  * @}
  */

/** @addtogroup FLASH_Registers_Bits_Definition
  * @{
  */
#define FLASH_CR1_HALT           ((u8)0x08) /*!< Standby in Halt mode Mask */
#define FLASH_CR1_AHALT          ((u8)0x04) /*!< Standby in Active Halt mode Mask */
#define FLASH_CR1_IE             ((u8)0x02) /*!< Flash Interrupt enable Mask */
#define FLASH_CR1_FIX            ((u8)0x01) /*!< Fix programming time Mask */

#define FLASH_CR2_OPT            ((u8)0x80) /*!< Select option byte Mask */
#define FLASH_CR2_WWO            ((u8)0x40) /*!< Word write once Mask */
#define FLASH_CR2_ERASE          ((u8)0x20) /*!< Erase block Mask */
#define FLASH_CR2_FPRG           ((u8)0x10) /*!< Fast programming mode Mask */
#define FLASH_CR2_PRG            ((u8)0x01) /*!< Program block Mask */

#define FLASH_NCR2_NOPT          ((u8)0x80) /*!< Select option byte Mask */
#define FLASH_NCR2_NWWO          ((u8)0x40) /*!< Word write once Mask */
#define FLASH_NCR2_NERASE        ((u8)0x20) /*!< Erase block Mask */
#define FLASH_NCR2_NFPRG         ((u8)0x10) /*!< Fast programming mode Mask */
#define FLASH_NCR2_NPRG          ((u8)0x01) /*!< Program block Mask */

#define FLASH_FPR_FWP            ((u8)0xFF) /*!< Boot memory size Mask */

#define FLASH_NFPR_NFWP          ((u8)0xFF) /*!< Boot memory size Mask */

#define FLASH_IAPSR_ENDHV        ((u8)0x40) /*!< End of high voltage flag Mask */
#define FLASH_IAPSR_SOP          ((u8)0x20) /*!< Start of operation flag Mask */
#define FLASH_IAPSR_ECCF         ((u8)0x10) /*!< ECC correction flag Mask */
#define FLASH_IAPSR_DATAUNLOCKED ((u8)0x08) /*!< Data EEPROM unlocked flag Mask */
#define FLASH_IAPSR_EOP          ((u8)0x04) /*!< End of operation flag Mask */
#define FLASH_IAPSR_PRGUNLOCKED  ((u8)0x02) /*!< Program memory unlocked flag Mask */
#define FLASH_IAPSR_WR_PG_DIS    ((u8)0x01) /*!< Write attempted to protected page Mask */

#define FLASH_PUNPR_PUNP         ((u8)0xFF) /*!< Program memory unprotection Mask */

#define FLASH_DUNPR_DUNP         ((u8)0xFF) /*!< Data EEPROM unprotection Mask */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Option Bytes (OPT)
  */
typedef volatile struct OPT_struct
{
  u8 OPT0;  /*!< Option byte 0 */ 
  u8 NOPT0; /*!< Complementary Option byte 0 */
  u8 OPT1;  /*!< Option byte 1 */ 
  u8 NOPT1; /*!< Complementary Option byte 1 */
  u8 OPT2;  /*!< Option byte 2 */
  u8 NOPT2; /*!< Complementary Option byte 2 */
  u8 OPT3;  /*!< Option byte 3 */
  u8 NOPT3; /*!< Complementary Option byte 3 */
} OPT_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief Internal Low Speed Watchdog (IWDG)
  */
typedef volatile struct IWDG_struct
{
  u8 KR;  /* Low Speed Watchdog Key Register */
  u8 PR;  /* Low Speed Watchdog Prescaler Register */
  u8 RLR; /* Low Speed Watchdog Reload Register */
}
IWDG_TypeDef;

/** @addtogroup IWDG_Registers_Reset_Value
  * @{
  */
#define IWDG_RLR_RESET_VALUE    ((u8)0xFF)  /*! <Reload Register Default Value */
#define IWDG_PR_RESET_VALUE     ((u8)0x00)  /*! <Prescaler Register Default Value */
/**
  * @}
  */
  
/*----------------------------------------------------------------------------*/
/**
  * @brief Window Watchdog (WWDG)
  */
typedef volatile struct WWDG_struct
{	
  u8 CR;  /* Watchdog Control Register  */
  u8 WR;  /* Window Watchdog  Register  */
}
WWDG_TypeDef;

/** @addtogroup WWDG_Registers_Reset_Value
  * @{
  */
#define WWDG_CR_RESET_VALUE		((u8)0x7F)	/*! <Control Register Default Value */
#define WWDG_WR_RESET_VALUE		((u8)0x7F)	/*! <Window Register Default Value */
/**
  * @}
  */
  
/** @addtogroup WWDG_Registers_Bits_Definition
  * @{
  */
#define WWDG_CR_WDGA		((u8)0x80)		/*!< WDGA bit mask */
#define WWDG_CR_T6			((u8)0x40)		/*!< T6 bit mask */
#define WWDG_CR_T				((u8)0x7F)		/*!< T bits mask */
#define WWDG_WR_MSB			((u8)0x80)		/*!< MSB bit mask */
#define WWDG_WR_W				((u8)0x7F)		/*!< W bits mask */  
/**
  * @}
  */


/*----------------------------------------------------------------------------*/
/**
  * @brief Reset Controller (RST)
  */
typedef volatile struct RST_struct
{
  u8 STAT;  /*  RESET CONTROL STATUS REGISTER   */
  u8 HPTRIM;  /*  RESET CONTROL HPTRIM REGISTER   */
  u8 HPTRIM_C;   /*   RESET CONTROL HPTRIM_C REGISTER  */
  u8 LPTRIM;  /*  RESET CONTROL LPTRIM REGISTER   */
  u8 LPTRIM_C;   /*  RESET CONTROL LPTRIM_C REGISTER  */
}
RST_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief Serial Peripheral Interface (SPI)
  */
typedef volatile struct SPI_struct
{
  u8 CR1; 		/* SPI control register 1 */
  u8 CR2; 		/* SPI control register 2 */
  u8 ICR; 		/* SPI interrupt control register */
  u8 SR;  		/* SPI status register */
  u8 DR;  		/* SPI data I/O register */
  u8 CRCPR; 	/* SPI CRC polynomial register*/
  u8 RXCRCR;  /* SPI Rx CRC register */
  u8 TXCRCR;  /* SPI Tx CRC register */
}
SPI_TypeDef;

/** @addtogroup SPI_Registers_Reset_Value
  * @{
  */
	#define SPI_CR1_RESET_VALUE			((u8)0x00)	/*! <Control Register 1 reset value */
	#define SPI_CR2_RESET_VALUE			((u8)0x00)	/*! <Control Register 2 reset value */
	#define SPI_ICR_RESET_VALUE			((u8)0x00)	/*! <Interrupt Control Register reset value */
	#define SPI_SR_RESET_VALUE			((u8)0x02)	/*! <Status Register reset value */
	#define SPI_DR_RESET_VALUE			((u8)0x00)	/*! <Data Register reset value */
	#define SPI_CRCPR_RESET_VALUE		((u8)0x07)	/*! <Polynomial Register reset value */
	#define SPI_CRCR_RESET_VALUE		((u8)0xFF)	/*! <CRC Register reset value */
	#define SPI_RXCRCR_RESET_VALUE	((u8)0xFF)	/*! <RX CRC Register reset value */
	#define SPI_TXCRCR_RESET_VALUE	((u8)0xFF)	/*! <TX CRC Register reset value */

/**
  * @}
  */
  
/** @addtogroup SPI_Registers_Bits_Definition
  * @{
  */
  #define SPI_ICR_TXIE				((u8)0x80)		/*!< Tx buffer empty interrupt enable bits mask */
  #define SPI_ICR_RXIE				((u8)0x40)		/*!< Rx buffer empty interrupt enable bits mask */
  #define SPI_ICR_ERRIE				((u8)0x20)		/*!< Error interrupt enable bits mask */
  #define SPI_ICR_WKIE				((u8)0x10)		/*!< Wake-up interrupt enable bits mask */
  
  #define SPI_CR2_BIDIMODE		((u8)0x80)		/*!< Bi-directional data mode enable bits mask */
  #define SPI_CR2_BIDIOE			((u8)0x40)		/*!< Output enable in bi-directional mode bits mask */
  #define SPI_CR2_CRCEN				((u8)0x20)		/*!< Hardware CRC calculation enable bits mask */
  #define SPI_CR2_CRCNEXT			((u8)0x10)		/*!< Transmit CRC next bits mask */
  #define SPI_CR2_SSM					((u8)0x02)		/*!< Software slave managment bits mask */
  #define SPI_CR2_SSI					((u8)0x01)		/*!< Internal slave select bits mask */
  
  #define SPI_CR1_SPE					((u8)0x40)		/*!< SPI enable bits mask */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief SWIM
  */
typedef volatile struct SWIM_struct
{
  u8 CSR; /* Control/Status register  */
  u8 DR;  /* Data register */
}
SWIM_TypeDef;

/*----------------------------------------------------------------------------*/
/**
  * @brief USART 
  */
typedef volatile struct USART_struct
{
  u8 SR;  /* USART status register  */
  u8 DR;  /* USART data register     */
  u8 BRR1;  /* USART baud rate register   */
  u8 BRR2;  /* USART DIV mantissa[11:8] SCIDIV fraction */
  u8 CR1;  /* USART control register 1     */
  u8 CR2;  /* USART control register 2     */
  u8 CR3;  /* USART control register 3      */
  u8 CR4;  /* USART control register 4      */
  u8 CR5;  /* USART control register 5       */
  u8 GT;  /* USART guard time register     */
  u8 PSCR;  /* USART prescaler register     */
}
USART_TypeDef;


/** @addtogroup USART_Registers_Reset_Value
  * @{
  */
#define	USART_SR_RESET_VALUE ((u8)0xC0)
#define	USART_BRR1_RESET_VALUE ((u8)0x00)
#define	USART_BRR2_RESET_VALUE ((u8)0x00)
#define	USART_CR1_RESET_VALUE ((u8)0x00)
#define	USART_CR2_RESET_VALUE ((u8)0x00)