#define AT91C_EMAC_CLRSTAT    (0x1 << 5 ) /**< (EMAC) Clear statistics registers.  */
#define AT91C_EMAC_INCSTAT    (0x1 << 6 ) /**< (EMAC) Increment statistics registers.  */
#define AT91C_EMAC_WESTAT     (0x1 << 7 ) /**< (EMAC) Write enable for statistics registers.  */
#define AT91C_EMAC_BP         (0x1 << 8 ) /**< (EMAC) Back pressure.  */
#define AT91C_EMAC_TSTART     (0x1 << 9 ) /**< (EMAC) Start Transmission.  */
#define AT91C_EMAC_THALT      (0x1 << 10) /**< (EMAC) Transmission Halt.  */
#define AT91C_EMAC_TPFR       (0x1 << 11) /**< (EMAC) Transmit pause frame  */
#define AT91C_EMAC_TZQ        (0x1 << 12) /**< (EMAC) Transmit zero quantum pause frame */
/* --- Register EMAC_NCFGR */
#define AT91C_EMAC_SPD        (0x1 << 0 ) /**< (EMAC) Speed.  */
#define AT91C_EMAC_FD         (0x1 << 1 ) /**< (EMAC) Full duplex.  */
#define AT91C_EMAC_JFRAME     (0x1 << 3 ) /**< (EMAC) Jumbo Frames.  */
#define AT91C_EMAC_CAF        (0x1 << 4 ) /**< (EMAC) Copy all frames.  */
#define AT91C_EMAC_NBC        (0x1 << 5 ) /**< (EMAC) No broadcast.  */
#define AT91C_EMAC_MTI        (0x1 << 6 ) /**< (EMAC) Multicast hash event enable */
#define AT91C_EMAC_UNI        (0x1 << 7 ) /**< (EMAC) Unicast hash enable.  */
#define AT91C_EMAC_BIG        (0x1 << 8 ) /**< (EMAC) Receive 1522 bytes.  */
#define AT91C_EMAC_EAE        (0x1 << 9 ) /**< (EMAC) External address match enable.  */
#define AT91C_EMAC_CLK        (0x3 << 10) /**< (EMAC)  */
#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) /**< (EMAC) HCLK divided by 8 */
#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) /**< (EMAC) HCLK divided by 16 */
#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) /**< (EMAC) HCLK divided by 32 */
#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) /**< (EMAC) HCLK divided by 64 */
#define AT91C_EMAC_RTY        (0x1 << 12) /**< (EMAC)  */
#define AT91C_EMAC_PAE        (0x1 << 13) /**< (EMAC)  */
#define AT91C_EMAC_RBOF       (0x3 << 14) /**< (EMAC)  */
#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) /**< (EMAC) no offset from start of receive buffer */
#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) /**< (EMAC) one byte offset from start of receive buffer */
#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) /**< (EMAC) two bytes offset from start of receive buffer */
#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) /**< (EMAC) three bytes offset from start of receive buffer */
#define AT91C_EMAC_RLCE       (0x1 << 16) /**< (EMAC) Receive Length field Checking Enable */
#define AT91C_EMAC_DRFCS      (0x1 << 17) /**< (EMAC) Discard Receive FCS */
#define AT91C_EMAC_EFRHD      (0x1 << 18) /**< (EMAC)  */
#define AT91C_EMAC_IRXFCS     (0x1 << 19) /**< (EMAC) Ignore RX FCS */
/* --- Register EMAC_NSR */
#define AT91C_EMAC_LINKR      (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_MDIO       (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_IDLE       (0x1 << 2 ) /**< (EMAC)  */
/* --- Register EMAC_TSR */
#define AT91C_EMAC_UBR        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_COL        (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_RLES       (0x1 << 2 ) /**< (EMAC)  */
#define AT91C_EMAC_TGO        (0x1 << 3 ) /**< (EMAC) Transmit Go */
#define AT91C_EMAC_BEX        (0x1 << 4 ) /**< (EMAC) Buffers exhausted mid frame */
#define AT91C_EMAC_COMP       (0x1 << 5 ) /**< (EMAC)  */
#define AT91C_EMAC_UND        (0x1 << 6 ) /**< (EMAC)  */
/* --- Register EMAC_RSR */
#define AT91C_EMAC_BNA        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_REC        (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_OVR        (0x1 << 2 ) /**< (EMAC)  */
/* --- Register EMAC_ISR */
#define AT91C_EMAC_MFD        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_RCOMP      (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_RXUBR      (0x1 << 2 ) /**< (EMAC)  */
#define AT91C_EMAC_TXUBR      (0x1 << 3 ) /**< (EMAC)  */
#define AT91C_EMAC_TUNDR      (0x1 << 4 ) /**< (EMAC)  */
#define AT91C_EMAC_RLEX       (0x1 << 5 ) /**< (EMAC)  */
#define AT91C_EMAC_TXERR      (0x1 << 6 ) /**< (EMAC)  */
#define AT91C_EMAC_TCOMP      (0x1 << 7 ) /**< (EMAC)  */
#define AT91C_EMAC_LINK       (0x1 << 9 ) /**< (EMAC)  */
#define AT91C_EMAC_ROVR       (0x1 << 10) /**< (EMAC)  */
#define AT91C_EMAC_HRESP      (0x1 << 11) /**< (EMAC)  */
#define AT91C_EMAC_PFRE       (0x1 << 12) /**< (EMAC)  */
#define AT91C_EMAC_PTZ        (0x1 << 13) /**< (EMAC)  */
/* --- Register EMAC_IER */
#define AT91C_EMAC_MFD        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_RCOMP      (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_RXUBR      (0x1 << 2 ) /**< (EMAC)  */
#define AT91C_EMAC_TXUBR      (0x1 << 3 ) /**< (EMAC)  */
#define AT91C_EMAC_TUNDR      (0x1 << 4 ) /**< (EMAC)  */
#define AT91C_EMAC_RLEX       (0x1 << 5 ) /**< (EMAC)  */
#define AT91C_EMAC_TXERR      (0x1 << 6 ) /**< (EMAC)  */
#define AT91C_EMAC_TCOMP      (0x1 << 7 ) /**< (EMAC)  */
#define AT91C_EMAC_LINK       (0x1 << 9 ) /**< (EMAC)  */
#define AT91C_EMAC_ROVR       (0x1 << 10) /**< (EMAC)  */
#define AT91C_EMAC_HRESP      (0x1 << 11) /**< (EMAC)  */
#define AT91C_EMAC_PFRE       (0x1 << 12) /**< (EMAC)  */
#define AT91C_EMAC_PTZ        (0x1 << 13) /**< (EMAC)  */
/* --- Register EMAC_IDR */
#define AT91C_EMAC_MFD        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_RCOMP      (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_RXUBR      (0x1 << 2 ) /**< (EMAC)  */
#define AT91C_EMAC_TXUBR      (0x1 << 3 ) /**< (EMAC)  */
#define AT91C_EMAC_TUNDR      (0x1 << 4 ) /**< (EMAC)  */
#define AT91C_EMAC_RLEX       (0x1 << 5 ) /**< (EMAC)  */
#define AT91C_EMAC_TXERR      (0x1 << 6 ) /**< (EMAC)  */
#define AT91C_EMAC_TCOMP      (0x1 << 7 ) /**< (EMAC)  */
#define AT91C_EMAC_LINK       (0x1 << 9 ) /**< (EMAC)  */
#define AT91C_EMAC_ROVR       (0x1 << 10) /**< (EMAC)  */
#define AT91C_EMAC_HRESP      (0x1 << 11) /**< (EMAC)  */
#define AT91C_EMAC_PFRE       (0x1 << 12) /**< (EMAC)  */
#define AT91C_EMAC_PTZ        (0x1 << 13) /**< (EMAC)  */
/* --- Register EMAC_IMR */
#define AT91C_EMAC_MFD        (0x1 << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_RCOMP      (0x1 << 1 ) /**< (EMAC)  */
#define AT91C_EMAC_RXUBR      (0x1 << 2 ) /**< (EMAC)  */
#define AT91C_EMAC_TXUBR      (0x1 << 3 ) /**< (EMAC)  */
#define AT91C_EMAC_TUNDR      (0x1 << 4 ) /**< (EMAC)  */
#define AT91C_EMAC_RLEX       (0x1 << 5 ) /**< (EMAC)  */
#define AT91C_EMAC_TXERR      (0x1 << 6 ) /**< (EMAC)  */
#define AT91C_EMAC_TCOMP      (0x1 << 7 ) /**< (EMAC)  */
#define AT91C_EMAC_LINK       (0x1 << 9 ) /**< (EMAC)  */
#define AT91C_EMAC_ROVR       (0x1 << 10) /**< (EMAC)  */
#define AT91C_EMAC_HRESP      (0x1 << 11) /**< (EMAC)  */
#define AT91C_EMAC_PFRE       (0x1 << 12) /**< (EMAC)  */
#define AT91C_EMAC_PTZ        (0x1 << 13) /**< (EMAC)  */
/* --- Register EMAC_MAN */
#define AT91C_EMAC_DATA       (0xFFFF << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_CODE       (0x3 << 16) /**< (EMAC)  */
#define AT91C_EMAC_REGA       (0x1F << 18) /**< (EMAC)  */
#define AT91C_EMAC_PHYA       (0x1F << 23) /**< (EMAC)  */
#define AT91C_EMAC_RW         (0x3 << 28) /**< (EMAC)  */
#define AT91C_EMAC_SOF        (0x3 << 30) /**< (EMAC)  */
/* --- Register EMAC_USRIO */
#define AT91C_EMAC_RMII       (0x1 << 0 ) /**< (EMAC) Reduce MII */
#define AT91C_EMAC_CLKEN      (0x1 << 1 ) /**< (EMAC) Clock Enable */
/* --- Register EMAC_WOL */
#define AT91C_EMAC_IP         (0xFFFF << 0 ) /**< (EMAC) ARP request IP address */
#define AT91C_EMAC_MAG        (0x1 << 16) /**< (EMAC) Magic packet event enable */
#define AT91C_EMAC_ARP        (0x1 << 17) /**< (EMAC) ARP request event enable */
#define AT91C_EMAC_SA1        (0x1 << 18) /**< (EMAC) Specific address register 1 event enable */
#define AT91C_EMAC_MTI        (0x1 << 19) /**< (EMAC) Multicast hash event enable */
/* --- Register EMAC_REV */
#define AT91C_EMAC_REVREF     (0xFFFF << 0 ) /**< (EMAC)  */
#define AT91C_EMAC_PARTREF    (0xFFFF << 16) /**< (EMAC)  */

#endif /* __AT91SAM7X256_EMAC_H */