/*   Do *not* directly modify this file.  It was    *//*   generated by the Configuration Tool; any  *//*   changes risk being overwritten.                *//* INPUT sound.cdb *//*  Include Header File  */#include "soundcfg.h"#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")#include <csl_chiphal.h>/*  Config Structures */EMIF_Config emifCfg0 = {    0x02a0,        /*  Global Control Register   */    0x0000,        /*  Global Reset Register   */    0x3fff,        /*  CE0 Space Control Register 1   */    0x5fff,        /*  CE0 Space Control Register 2   */    0x5fff,        /*  CE0 Space Control Register 3   */    0x2fff,        /*  CE1 Space Control Register 1   */    0x5fff,        /*  CE1 Space Control Register 2   */    0x5fff,        /*  CE1 Space Control Register 3   */    0x2fff,        /*  CE2 Space Control Register 1   */    0x5fff,        /*  CE2 Space Control Register 2   */    0x5fff,        /*  CE2 Space Control Register 3   */    0x2fff,        /*  CE3 Space Control Register 1   */    0x5fff,        /*  CE3 Space Control Register 2   */    0x5fff,        /*  CE3 Space Control Register 3   */    0xf948,        /*  SDRAM Control Register 1   */    0x0080,        /*  SDRAM Period Register   */    0x0fff,        /*  SDRAM Initialization Register   */    0x03ff         /*  SDRAM Control Register 2   */};MCBSP_Config mcbspCfg0 = {    0x0000,        /*  Serial Port Control Register 1   */    0x0000,        /*  Serial Port Control Register 2   */    0x0000,        /*  Receive Control Register 1   */    0x0000,        /*  Receive Control Register 2   */    0x0000,        /*  Transmit Control Register 1   */    0x0000,        /*  Transmit Control Register 2   */    0x0000,        /*  Sample Rate Generator Register 1   */    0x0000,        /*  Sample Rate Generator Register 2   */    0x0000,        /*  Multichannel Control Register 1   */    0x0000,        /*  Multichannel Control Register 2   */    0x0000,        /*  Pin Control Register   */    0x0000,        /*  Receive Channel Enable Register Partition A   */    0x0000,        /*  Receive Channel Enable Register Partition B   */    0x0000,        /*  Receive Channel Enable Register Partition C   */    0x0000,        /*  Receive Channel Enable Register Partition D   */    0x0000,        /*  Receive Channel Enable Register Partition E   */    0x0000,        /*  Receive Channel Enable Register Partition F   */    0x0000,        /*  Receive Channel Enable Register Partition G   */    0x0000,        /*  Receive Channel Enable Register Partition H   */    0x0000,        /*  Transmit Channel Enable Register Partition A   */    0x0000,        /*  Transmit Channel Enable Register Partition B   */    0x0000,        /*  Transmit Channel Enable Register Partition C   */    0x0000,        /*  Transmit Channel Enable Register Partition D   */    0x0000,        /*  Transmit Channel Enable Register Partition E   */    0x0000,        /*  Transmit Channel Enable Register Partition F   */    0x0000,        /*  Transmit Channel Enable Register Partition G   */    0x0000         /*  Transmit Channel Enable Register Partition H   */};PLL_Config pllCfg0 = {    0x0000,        /*  PLL Response After Idle (IAI)   */    0x0000,        /*  Response to Loss of PLL Core Lock (IOB)   */    0x0005,        /*  PLL Multiply Value (PLL_MULT)   */    0x0000         /*  PLL Divide Value (PLL_DIV)   */};/*  Handles  */MCBSP_Handle hMcbsp0;MCBSP_Handle hMcbsp1;MCBSP_Handle hMcbsp2;/* *  ======== CSL_cfgInit() ========   */void CSL_cfgInit(){        CHIP_RSET(XBSR, 1);    hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);    hMcbsp1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);    hMcbsp2 = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);            MCBSP_config(hMcbsp0, &mcbspCfg0);    PLL_config(&pllCfg0);    /* You must use DMA_start() in your main code to start the DMA. */	        /* You must use MCBSP_start() in your main code to start the MCBSP. */        /* You must use RTC_start() in your main code to start the RTC. */        /* You must use WDTIM_start() in your main code to start the WDTIM. */}