?? start900.lst
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A51 MACRO ASSEMBLER START900 01/16/2008 09:07:59 PAGE 1
MACRO ASSEMBLER A51 V7.10
OBJECT MODULE PLACED IN START900.OBJ
ASSEMBLER INVOKED BY: d:\Keil\C51\BIN\A51.EXE START900.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;------------------------------------------------------------------------------
2 ; This file is part of the C51 Compiler package
3 ; Startup Code for the Philips LPC9xx devices
4 ; Copyright (c) 1988-2004 Keil Elektronik GmbH and Keil Software, Inc.
5 ; Version 2.3
6 ;
7 ; *** <<< Use Configuration Wizard in Context Menu >>> ***
8 ;------------------------------------------------------------------------------
9 ; START900.A51: This code is executed after processor reset.
10 ; You may add this file to a uVision2 project.
11 ;
12 ; To translate this file use Ax51 with the following invocation:
13 ;
14 ; Ax51 START900.A51 "your options"
15 ;
16 ; To link the modified START900.OBJ file to your application use the following
17 ; Lx51 invocation:
18 ;
19 ; Lx51 your object file list, START900.OBJ controls
20 ;
21 ;------------------------------------------------------------------------------
22 ;
23 ; User-defined <h> Power-On Initialization of Memory
24 ;
25 ; With the following statements the initialization of memory
26 ; at processor reset can be defined:
27 ;
28 ;<o> IDATA memory length <0x0-0x100>
29 ;<i> Notes: The absolute start-address of IDATA memory is always 0
30 ;<i> The IDATA space overlaps physically the DATA and BIT areas of the
31 ;<i> LPC9xx device.
0100 32 IDATALEN EQU 0x100 ; the length of IDATA memory in bytes.
33 ;
34 ; <o> XDATA memory start address <0x0-0xFFFF>
35 ; <i>the absolute start-address of XDATA memory
0000 36 XDATASTART EQU 0
37 ;
38 ; <o> XDATA memory length <0x0-0xFFFF>
39 ; <i>the length of XDATA memory in bytes.
0000 40 XDATALEN EQU 0
41 ;
42 ; </h>
43 ;------------------------------------------------------------------------------
44 ;
45 ; <h> Reentrant Stack Initilization
46 ;
47 ; The following EQU statements define the stack pointer for reentrant
48 ; functions and initialized it:
49 ;
50 ; Stack Space for reentrant functions in the SMALL model.
51 ; <e> Activate reentrant Stack (SMALL model)
0000 52 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
53 ; <o> top of stack <0x0-0x100>
54 ; <i> set top of stack to highest location+1
0100 55 IBPSTACKTOP EQU 0x100 ; default 0FFH+1
56 ; </e>
57 ; Stack Space for reentrant functions in the LARGE model.
58 ; <e> Activate reentrant Stack (LARGE model)
A51 MACRO ASSEMBLER START900 01/16/2008 09:07:59 PAGE 2
0000 59 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
60 ; <o> top of stack <0x0-0x200>
61 ; <i> set top of stack to highest location+1.
01FF 62 XBPSTACKTOP EQU 0x1FF ; default 01FFH+1
63 ; </e>
64 ;
65 ; Stack Space for reentrant functions in the COMPACT model.
66 ; <e> Activate reentrant Stack (COMPACT model)
0000 67 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
68 ; <o> top of stack <0x0-0x100>
69 ; <i> set top of stack to highest location+1.
0100 70 PBPSTACKTOP EQU 0x100 ; default 0FFH+1
71 ; </e>
72 ; </h>
73 ;------------------------------------------------------------------------------
74 ;
75 ; Setup LPC9xx Configuration Register (UCFG1, BOOTVEC, BOOTSTAT, SEC0..SEC7)
76 ; <h> Configuration UCFG1
77 ; Oscillator Configuration (UCFG1.0 .. UCFG1.2)
78 ; <o> FOSC: (UCFG1.0 .. UCFG1.2)
79 ; FOCS Val Description
80 ; -------- -----------
81 ; <0=> high frequency crystal or resonator (4MHz .. 20MHz)
82 ; <1=> medium frequency crystal or resonator (100kHz .. 4MHz)
83 ; <2=> low frequency crystal (20kHz .. 100kHz)
84 ; <3=> internal RC oscillator (7.373MHz +/- 2.5 percent)
85 ; <4=> internal Watchdog oscillator (400kHz +20/-30 percent)
86 ; <7=> external clock input on X1
87 ; <i> Oscillator Configuration
0003 88 FOSC EQU 3 ; default on unprogrammed parts: 3 = internal RC oscillator
89
90 ; <o> WDSE: (UCFG1.4)
91 ; WDSE Val Description
92 ; -------- -----------
93 ; <0=> User can set WDT-Osc. as clock source
94 ; <1=> WDT is running with WDT-Osc.
95 ; <i> Watchdog Saftey Enable (0 = default on unprogrammed part)
0000 96 WDSE EQU 0 ; 0 = user can set WDCLK to select clock source(default on unprogrammed part)
97 ;
98 ; <o> BOE: (UCFG1.5)
99 ; BOE Val Description
100 ; ------- -----------
101 ; <0=> Disable
102 ; <1=> Enable
103 ; <i> Brownout Detect Enable (1 = default on unprogrammed part)
0001 104 BOE EQU 1
105 ;
106 ; <o> RPE: (UCFG1.6)
107 ; RPE Val Description
108 ; -------- -----------
109 ; <0=> Disable (P1.5 can use as input pin)
110 ; <1=> Enable (P1.5 used as reset pin)
111 ; <i> Reset PIN enable (0 = default on unprogrammed part)
0000 112 RPE EQU 0
113 ;
114 ; <o> WDTE: (UCFG1.7)
115 ; WDTE Val Description
116 ; -------- -----------
117 ; <0=> Disable (WDSE has no effect)
118 ; <1=> Enable
119 ; <i> Watchdog timer enable (0 = default on unprogrammed part)
0000 120 WDTE EQU 0
121 ; </h>
122 ;
123 ; <h> Boot Program
124 ; <o> BSB: (BOOTSTAT.0)
A51 MACRO ASSEMBLER START900 01/16/2008 09:07:59 PAGE 3
125 ; BSB Val Description
126 ; ------- -----------
127 ; <0=> Disable ISP entry on power-up
128 ; <1=> Enable ISP entry on power-up
129 ; <i> enables In-System Programming (ISP) power-up
0000 130 BOOTSTAT EQU 0
131 ;
132 ;
133 ; BOOTVECTOR (BOOTVEC)
134 ; --------------------
135 ; <o> ISP entry point <0x0-0x1F00:0x100> <# /0x100>
136 ; <i> points to ISP entry point (default c:0x1E00 on unprogrammed part)
001E 137 BOOTVEC EQU 0x1E ;
138 ; </h>
139 ;
140 ; <h> Flash Security Configuration
141 ; <h> SECO: (SEC0.0 .. SEC0.2)
142 ; SEC0 Val Description
143 ; -------- -----------
144 ; <q.0> Disable reading with MOVC
145 ; <q.1> Disable program/erase
146 ; <q.2> Disable IAP/ISP global erase
147 ; <i> Flash Security Configuration sector 0 (c:0x0000 - c:0x03FF)
0000 148 SEC0 EQU 0
149 ; </h>
150
151 ; <h> SEC1: (SEC1.0 .. SEC1.2)
152 ; SEC1 Bit Description
153 ; -------- -----------
154 ; <q.0> Disable reading with MOVC
155 ; <q.1> Disable program/erase
156 ; <q.2> Disable IAP/ISP global erase
157 ; <i> Flash Security Configuration sector 0 (c:0x0400 - c:0x07FF)
0000 158 SEC1 EQU 0
159 ; </h>
160
161 ; <h> SEC2: (SEC2.0 .. SEC2.2)
162 ; SEC2 Bit Description
163 ; -------- -----------
164 ; <q.0> Disable reading with MOVC
165 ; <q.1> Disable program/erase
166 ; <q.2> Disable IAP/ISP global erase
167 ; <i> Flash Security Configuration sector 0 (c:0x0800 - c:0x0BFF)
0000 168 SEC2 EQU 0
169 ; </h>
170
171 ; <h> SEC3: (SEC3.0 .. SEC3.2)
172 ; SEC3 Bit Description
173 ; -------- -----------
174 ; <q.0> Disable reading with MOVC
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