?? 波形信號發生器程序.txt
字號:
EDA部分
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library IEEE; --頂層文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ddsa is
port(sysclk:in std_logic;
sel:in std_logic_vector(1 downto 0);
selok:in std_logic;
fpin:in std_logic_vector(7 downto 0);
ddsout1:out std_logic_vector(7 downto 0);
ddsout2:out std_logic_vector(7 downto 0));
end ddsa;
architecture Behavioral of ddsa is
component ddsall is
port ( sysclk:in std_logic;
selok:in std_logic;
ddsout:out std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
fpin:in std_logic_vector(7 downto 0));
end component;
component ddsall1 is
port ( sysclk:in std_logic;
ddsout:out std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
fpin:in std_logic_vector(7 downto 0));
end component;
signal a,b,c:std_logic_vector(7 downto 0);
begin
a<=fpin;ddsout1<=b;ddsout2<=c;
u0: ddsall
PORT MAP( sysclk =>sysclk ,
ddsout =>b ,
sel =>sel ,
selok=>selok,
fpin =>a);
u1: ddsall1
PORT MAP(sysclk =>sysclk ,
ddsout => c,
sel =>sel ,
fpin =>a );
end Behavioral;
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鎖腳文件
NET "ddsout1<0>" LOC = "p29";
NET "ddsout1<1>" LOC = "p30";
NET "ddsout1<2>" LOC = "p31";
NET "ddsout1<3>" LOC = "p33";
NET "ddsout1<4>" LOC = "p34";
NET "ddsout1<5>" LOC = "p35";
NET "ddsout1<6>" LOC = "p36";
NET "ddsout1<7>" LOC = "p40";
NET "ddsout2<0>" LOC = "p3";
NET "ddsout2<1>" LOC = "p5";
NET "ddsout2<2>" LOC = "p7";
NET "ddsout2<3>" LOC = "p9";
NET "ddsout2<4>" LOC = "p11";
NET "ddsout2<5>" LOC = "p16";
NET "ddsout2<6>" LOC = "p18";
NET "ddsout2<7>" LOC = "p21";
NET "fpin<0>" LOC = "p163";
NET "fpin<1>" LOC = "p164";
NET "fpin<2>" LOC = "p165";
NET "fpin<3>" LOC = "p166";
NET "fpin<4>" LOC = "p167";
NET "fpin<5>" LOC = "p168";
NET "fpin<6>" LOC = "p169";
NET "fpin<7>" LOC = "p173";
NET "sysclk" LOC = "p80";
NET "selok" LOC = "p181";
NET "sel<1>" LOC = "p179";
NET "sel<0>" LOC = "p180";
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library IEEE; ---ddsc頂層文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ddsall is
port ( sysclk:in std_logic;
selok:in std_logic;
ddsout:out std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
fpin:in std_logic_vector(7 downto 0));
end ddsall;
architecture Behavioral of ddsall is
component ddsc is
generic( freq_width :integer :=24; --輸入頻率字位寬
phase_width :integer :=8; --輸入相位字位寬
adder_width:integer :=24; --累加器位寬
romad_width:integer :=8; --正弦ROM表地址位寬
rom_d_width:integer :=8); --正弦ROM表數據位寬
port ( clk :in std_logic;
freqin:in std_logic_vector(freq_width-1 downto 0); --頻率字輸入
phasein :in std_logic_vector(phase_width-1 downto 0); --相位字輸入
ddsout :out std_logic_vector(rom_d_width-1 downto 0)); --DDS輸出
end component ddsc;
signal freqind:std_logic_vector(23 downto 0);
signal phaseind:std_logic_vector(7 downto 0);
signal clk4:std_logic;
begin
u0: ddsc port map(clk=>clk4,ddsout=>ddsout,phasein=>phaseind,freqin=>freqind);
process(sysclk)
variable cnt:integer range 0 to 8;
begin
if sysclk'event and sysclk='1'then
cnt:=cnt+1;
if cnt<4 then clk4<='1';
elsif cnt<8 then clk4<='0';
else cnt:=0; clk4<='0';
end if;
end if;
end process;
process(clk4)
begin
if (clk4'event and clk4='1')then
if sel="01" then
freqind(23 downto 16)<=fpin;
elsif sel="10"then
freqind(15 downto 8)<=fpin;
elsif sel="00"then
freqind(7 downto 0)<=fpin;
elsif selok='0'then
phaseind<=fpin;
end if;
end if;
end process;
end Behavioral;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
library IEEE; --DDS主模塊
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ddsc is
generic( freq_width :integer :=24; --輸入頻率字位寬
phase_width :integer :=8; --輸入相位字位寬
adder_width:integer :=24; --累加器位寬
romad_width:integer :=8; --正弦ROM表地址位寬
rom_d_width:integer :=8); --正弦ROM表數據位寬
port ( clk :in std_logic;
freqin:in std_logic_vector(freq_width-1 downto 0); --頻率字輸入
phasein :in std_logic_vector(phase_width-1 downto 0); --相位字輸入
ddsout :out std_logic_vector(rom_d_width-1 downto 0)); --DDS輸出
end entity ddsc;
architecture Behavioral of ddsc is
signal acc:std_logic_vector(adder_width-1 downto 0):="000000000000000000000000";
signal phaseadd:std_logic_vector(phase_width-1 downto 0);
signal romaddr:std_logic_vector(romad_width-1 downto 0);
signal freqw :std_logic_vector(freq_width-1 downto 0);
signal phasew:std_logic_vector(phase_width-1 downto 0);
component aa
port ( addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end component;
begin
process (clk)
begin
if clk'event and clk='1' then
phasew<=phasein;
freqw<=freqin;
acc<=acc+freqw;
end if;
end process;
phaseadd<=acc(adder_width-1 downto adder_width- phase_width) +phasew;
romaddr<=phaseadd(phase_width-1 downto phase_width-romad_width);
u1 : aa port map ( addr =>romaddr,clk => clk,dout => ddsout);
end Behavioral;
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library IEEE; ---數據頂層文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aa is
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end aa;
architecture Behavioral of aa is
component sin_rom
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end component;
begin
u0 : sin_rom port map (addr =>addr,clk => clk,dout => dout);
end Behavioral;
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library IEEE; --ddsc1頂層文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ddsall1 is
port ( sysclk:in std_logic;
ddsout:out std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
fpin:in std_logic_vector(7 downto 0));
end ddsall1;
architecture Behavioral of ddsall1 is
component ddsc1 is
generic( freq_width :integer :=24; --輸入頻率字位寬
phase_width :integer :=8; --輸入相位字位寬
adder_width:integer :=24; --累加器位寬
romad_width:integer :=8; --正弦ROM表地址位寬
rom_d_width:integer :=8); --正弦ROM表數據位寬
port ( clk :in std_logic;
freqin:in std_logic_vector(freq_width-1 downto 0); --頻率字輸入
phasein :in std_logic_vector(phase_width-1 downto 0); --相位字輸入
ddsout :out std_logic_vector(rom_d_width-1 downto 0));--DDS輸出
end component ddsc1;
signal freqind:std_logic_vector(23 downto 0);
signal phaseind:std_logic_vector(7 downto 0);
signal clk4:std_logic;
begin
u0: ddsc1 port map(clk=>clk4,ddsout=>ddsout,phasein=>phaseind,freqin=>freqind)
process(sysclk)
variable cnt:integer range 0 to 8;
begin
if sysclk'event and sysclk='1'then
cnt:=cnt+1;
if cnt<4 then clk4<='1';
elsif cnt<8 then clk4<='0';
else cnt:=0; clk4<='0';
end if;
end if;
end process;
process(clk4)
begin
if (clk4'event and clk4='1')then
if sel="01" then
freqind(23 downto 16)<=fpin;
elsif sel="10"then
freqind(15 downto 8)<=fpin;
elsif sel="00"then
freqind(7 downto 0)<=fpin;
end if;
phaseind<="00000000";
end if;
end process;
end Behavioral;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
library IEEE; --ddsc1頂層文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ddsall1 is
port ( sysclk:in std_logic;
ddsout:out std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
fpin:in std_logic_vector(7 downto 0));
end ddsall1;
architecture Behavioral of ddsall1 is
component ddsc1 is
generic( freq_width :integer :=24; --輸入頻率字位寬
phase_width :integer :=8; --輸入相位字位寬
adder_width:integer :=24; --累加器位寬
romad_width:integer :=8; --正弦ROM表地址位寬
rom_d_width:integer :=8); --正弦ROM表數據位寬
port ( clk:in std_logic;
freqin:in std_logic_vector(freq_width-1 downto 0); --頻率字輸入
phasein:in std_logic_vector(phase_width-1 downto 0); --相位字輸入
ddsout:out std_logic_vector(rom_d_width-1 downto 0)); --DDS輸出
end component ddsc1;
signal freqind:std_logic_vector(23 downto 0);
signal phaseind:std_logic_vector(7 downto 0);
signal clk4:std_logic;
begin
u0: ddsc1 port map(clk=>clk4,ddsout=>ddsout,phasein=>phaseind,freqin=>freqind);
process(sysclk)
variable cnt:integer range 0 to 8;
begin
if sysclk'event and sysclk='1'then
cnt:=cnt+1;
if cnt<4 then clk4<='1';
elsif cnt<8 then clk4<='0';
else cnt:=0; clk4<='0';
end if;
end if;
end process;
process(clk4)
begin
if (clk4'event and clk4='1')then
if sel="01" then
freqind(23 downto 16)<=fpin;
elsif sel="10"then
freqind(15 downto 8)<=fpin;
elsif sel="00"then
freqind(7 downto 0)<=fpin;
end if;
phaseind<="00000000";
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
library IEEE; --數據ROM文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aa1 is
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end aa1;
architecture Behavioral of aa1 is
component sin_rom1
port (addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0));
end component;
begin
u0 : sin_rom1 port map (addr =>addr,clk => clk,dout => dout);
end Behavioral;
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單片機部分
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;用AT89S52芯片
;/*資源分配:片內RAM ：80H~~~~FFH
; 棧 底：5FH
; 置數區 ：50H~~~~5EH
; 變量區 ：30H~~~~4FH
; 位尋此區：20H~~~~2FH
; 監控KEY
;74LS138的Y7作為8155的片選信號
FD8155 EQU 00H ; 8155命令口低8位地址
FG8155 EQU 0F0H ; 8155命令口高8位地址
AD8155 EQU 01H ; 8155PA口低8位地址
AG8155 EQU 0F0H ; 8155PA口高8位地址
BD8155 EQU 02H ; 8155PB口低8位地址
BG8155 EQU 0F0H ; 8155PB口高8位地址
CD8155 EQU 03H ; 8155PC口低8位地址
CG8155 EQU 0F0H ; 8155PC口高8位地址
KEYZHI EQU 2FH ;鍵值存放單元
CSA EQU P3.4 ;液晶片選在（左，前）顯示
CSB EQU P3.5 ;在（右、后）顯示
E EQU P3.3 ;使能信號
DI EQU P3.2 ;選擇存指令還是數據單元
COMSTART EQU 78H ;液晶的啟動
COMONOFF EQU 79H ;液晶開顯示
COMX EQU 7AH ;液晶的x軸
COMY EQU 7BH ;液晶的y軸
TABADDR EQU 7CH ;要顯示字符的表首地此
COMDATA EQU 7DH ;字符數據
JCS1CS2 EQU 7FH ;片選
ORG 0000H
START: LJMP MAIN
ORG 0030H
MAIN: MOV SP, #5FH;
MOV PSW, #00H;
MOV R0, #20H
MOV R7, #96
CLR A
LOOP: MOV @R0, A
INC R0
DJNZ R7, LOOP
LCALL CSH8155 ;8155初始化
MOV COMX,#0B8H
MOV COMY,#40H
LCALL CLEAR1 ;液晶清屏
MOV DPTR,#TAB0
MOV COMX,#0BAH
MOV COMY,#50H ;湖
MOV JCS1CS2,#00H
LCALL DISP
MOV DPTR,#TAB1
MOV COMX,#0BAH
MOV COMY,#60H ;南
MOV JCS1CS2,#00H
LCALL DISP
MOV DPTR,#TAB2
MOV COMX,#0BAH
MOV COMY,#70H ;工
MOV JCS1CS2,#00H
LCALL DISP
MOV DPTR,#TAB3
MOV COMX,#0BAH
MOV COMY,#40H ;學
MOV JCS1CS2,#01H
LCALL DISP
MOV DPTR,#TAB4
MOV COMX,#0BAH
MOV COMY,#50H ;院
MOV JCS1CS2,#01H
LCALL DISP
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