## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 20 18:35:51 中國標準時間 2007
##
vlib work
vcom -93 -explicit  qdq.vhdl
vcom -93 -explicit  ymq.vhdl
vcom -93 -explicit  bjq.vhdl
vcom -93 -explicit  dsq.vhdl
vcom -93 -explicit  fpq.vhdl
vcom -93 -explicit  top.vhf
vcom -93 -explicit  topaaa.vhd
vsim -t 1ps   -lib work testbench
do testbench.udo
view wave
add wave *
view structure
view signals
run 1000ns