-- VHDL Test Bench Created from source file fpq.vhd -- 11:00:35 06/11/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY fpq_fpqaaa_vhd_tb IS
END fpq_fpqaaa_vhd_tb;

ARCHITECTURE behavior OF fpq_fpqaaa_vhd_tb IS 

	COMPONENT fpq
	PORT(
		clkin : IN std_logic;          
		clkout : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clkin :  std_logic;
	SIGNAL clkout :  std_logic;

BEGIN

	uut: fpq PORT MAP(
		clkin => clkin,
		clkout => clkout
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      clkin<='0';wait for 15.625 ns;
	 clkin<='1';wait for 15.625 ns;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;