-- Vhdl test bench created from schematic top.sch - Wed May 30 16:35:15 2007
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT top
   PORT( qqd	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          out71	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          en1	:	IN	STD_LOGIC; 
          en	:	IN	STD_LOGIC; 
          clkin	:	IN	STD_LOGIC; 
          q	:	OUT	STD_LOGIC);
   END COMPONENT;

   SIGNAL qqd	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL out71	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL en1	:	STD_LOGIC;
   SIGNAL en	:	STD_LOGIC;
   SIGNAL clkin	:	STD_LOGIC;
   SIGNAL q	:	STD_LOGIC;

BEGIN

   UUT: top PORT MAP(
		qqd => qqd, 
		out71 => out71, 
		en1 => en1, 
		en => en, 
		clkin => clkin, 
		q => q
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      clkin<='1';wait for 15.625 ns;
	 clkin<='0';wait for 15.625 ns;
   END PROCESS;
   ta: process
    begin
       en1<='0';en<='0';wait for 10 ms;
	  en1<='1';wait;
	  end process;
    tc : process
    begin
       wait for 20 ms;
	  qqd<="00010000";
	  end process;
-- *** End Test Bench - User Defined Section ***

END;