-- Vhdl test bench created from schematic top.sch - Wed Jun 20 18:34:17 2007
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT top
   PORT( xuanshou	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          baojing	:	OUT	STD_LOGIC; 
          time1	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          time2	:	OUT	STD_LOGIC_VECTOR (6 DOWNTO 0); 
          en	:	IN	STD_LOGIC; 
          clk	:	IN	STD_LOGIC; 
          qd	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   SIGNAL xuanshou	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL baojing	:	STD_LOGIC;
   SIGNAL time1	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL time2	:	STD_LOGIC_VECTOR (6 DOWNTO 0);
   SIGNAL en	:	STD_LOGIC;
   SIGNAL clk	:	STD_LOGIC;
   SIGNAL qd	:	STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

   UUT: top PORT MAP(
		xuanshou => xuanshou, 
		baojing => baojing, 
		time1 => time1, 
		time2 => time2, 
		en => en, 
		clk => clk, 
		qd => qd
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
      BEGIN
       en<='0';wait for 10 ms;en<='1';
	  wait for 360 ms;en<='0';wait for 170 ms;
	  en<='1';wait;													

   END PROCESS;
   ta: process
   begin
      clk<='0';wait for 15.625 ns;
	 clk<='1';wait for 15.625 ns;
	 end process;
	  tc:process
	  begin
	    wait for 180 ms;qd<="00100000";wait for 20 ms;qd<="10000000";
	    wait for 20 ms;qd<="00000000";
	    wait for 10800 ms;qd<="00000100";
	    end process;
-- *** End Test Bench - User Defined Section ***

END;