/*""FILE COMMENT""*************************************************************
*       System Name : RENESAS T-Engine/micro T-Engine
*       File Name   : sh7145.h 
*       Version     : 1.00.00
*       Contents    : SH7145 Registers definition using T-Monitor
*       Model       : SH7145 micro T-Engine
*       CPU         : SH7145F
*       Compiler    : GNU/Renesas SH-C
*       OS          : T-Kernel
*       note        : The Software is being delivered to you "AS IS" 
*                   : and Renesas,whether explicitly or implicitly makes  
*                   : no warranty as to its Use or performance. 
*                   : RENESAS AND ITS SUPPLIER DO NOT AND CANNOT WARRANT 
*                   : THE PERFORMANCE OR RESULTS YOU MAY OBTAIN  BY USING 
*                   : THE SOFTWARE. AS TO ANY MATTER INCLUDING WITHOUT 
*                   : LIMITATION NONINFRINGEMENT OF THIRD PARTY RIGHTS,
*                   : MERCHANTABILITY, INTEGRATION, SATISFACTORY QUALITY, 
*                   : OR FITNESS FOR ANY PARTICULAR PURPOSE.
*
*       Copyright (c) 2004 RENESAS TECHNOLOGY CORP. All Rights Reserved.
*       AND RENESAS SOLUTIONS CORP. All Rights Reserved.
*
*       history     : 2006.03.27 ver.1.00.00
*""FILE COMMENT END""*********************************************************/

#ifndef _SH7145_H_
#define _SH7145_H_

/* module stand-by registers */
#define MSTCR1	((unsigned short *)0xffff861c)
#define MSTCR2	((unsigned short *)0xffff861e)

#define BCR1	((unsigned short *)0xffff8620)
#define BCR2	((unsigned short *)0xffff8622)
#define WCR1	((unsigned short *)0xffff8624)

#define PAIORH	(0xffff8384)
#define PAIORL	(0xffff8386)
#define PACRH	(0xffff8388)
#define PACRL1	(0xffff838c)
#define PACRL2	(0xffff838e)
#define PBIOR	(0xffff8394)
#define PCIOR	(0xffff8396)
#define PBCR1	(0xffff8398)
#define PBCR2	(0xffff839a)
#define PCCR	(0xffff839c)
#define PDIORH	(0xffff83a4)
#define PDIORL	(0xffff83a6)
#define PDCRH1	(0xffff83a8)
#define PDCRH2	(0xffff83aa)
#define PDCRL1	(0xffff83ac)
#define PDCRL2	(0xffff83ae)
#define PECRL1	(0xffff83b8)
#define PECRL2	(0xffff83ba)
#define PAIORL	(0xffff8386)
#define PBIOR	(0xffff8394)
#define PEIORL	(0xffff83b4)
#define PEDRL	(0xffff83b0)
#define PDDRH	0xffff83a0
#define PDDRL	0xffff83a2

/* Port Control Register */
#define PPCR	(0xffff87f8)

/* SCI */
#define SMR0	((unsigned char *)0xffff81a0)
#define BRR0	((unsigned char *)0xffff81a1)
#define SCR0	((unsigned char *)0xffff81a2)
#define TDR0	((unsigned char *)0xffff81a3)
#define SSR0	((unsigned char *)0xffff81a4)
#define RDR0	((unsigned char *)0xffff81a5)
#define SDCR0	((unsigned char *)0xffff81a6)

#define SMR1	(0xffff81b0)
#define BRR1	(0xffff81b1)
#define SCR1	(0xffff81b2)
#define TDR1	(0xffff81b3)
#define SSR1	(0xffff81b4)
#define RDR1	(0xffff81b5)
#define SDCR1	(0xffff81b6)

#define SMR2	(0xffff81c0)
#define BRR2	(0xffff81c1)
#define SCR2	(0xffff81c2)
#define TDR2	(0xffff81c3)
#define SSR2	(0xffff81c4)
#define RDR2	(0xffff81c5)
#define SDCR2	(0xffff81c6)

#define SMR3	(0xffff81d0)
#define BRR3	(0xffff81d1)
#define SCR3	(0xffff81d2)
#define TDR3	(0xffff81d3)
#define SSR3	(0xffff81d4)
#define RDR3	(0xffff81d5)
#define SDCR3	(0xffff81d6)

/* value for SCI */
#define SCR_TIE  0x80
#define SCR_RIE  0x40
#define SCR_TE   0x20
#define SCR_RE   0x10
#define SSR_ORER 0x20 /* overrun error */
#define SSR_FER  0x10 /* framing error */
#define SSR_PER  0x08 /* parity error  */
#define SSR_TDRE 0x80 /* Transmit ready */
#define SSR_RDRF 0x40 /* Receive full  */

/* IPR registers */
#define IPRA    (0xffff8348)
#define IPRB    (0xffff834a)
#define IPRC    (0xffff834c)
#define IPRD    (0xffff834e)
#define IPRE    (0xffff8350)
#define IPRF    (0xffff8352)
#define IPRG    (0xffff8354)
#define IPRH    (0xffff8356)
#define IPRI    (0xffff835c)
#define IPRJ    (0xffff835e)

#endif /* _SH7145_H_ */