?? hpi_dsp.asm
字號:
.mmregs
.global _c_int00
.global _init_54
.global _HPI_ISR
.global _Flag
result .set 0062h
num1 .set 0060h
num2 .set 0061h
.sect "vectors"
start: B _c_int00
NOP
NOP
nmi: B start
NOP
NOP
; software interrupts
sint17 .space 4*16
sint18 .space 4*16
sint19 .space 4*16
sint20 .space 4*16
sint21 .space 4*16
sint22 .space 4*16
sint23 .space 4*16
sint24 .space 4*16
sint25 .space 4*16
sint26 .space 4*16
sint27 .space 4*16
sint28 .space 4*16
sint29 .space 4*16
sint30 .space 4*16
int0: B start
nop
nop
int1: B start
nop
nop
int2: B start
NOP
NOP
tint0: B start
NOP
NOP
brint0: B start
nop
nop
bxint0: B start
NOP
NOP
NOP
DMAC0: B start
NOP
NOP
TINT1: B start
NOP
NOP
INT3: B start
NOP
NOP
hpint: _HPI_ISR
NOP
NOP
NOP
brint1: B start
NOP
NOP
NOP
bxint1: B start
NOP
NOP
DMAC4: B start
NOP
NOP
DMAC5: B start
NOP
NOP
.text
;>>>> interrupt
;***************************************************************
;* FUNCTION DEF: _HPI_ISR *
;***************************************************************
_HPI_ISR:
PSHM AL
PSHM AH
PSHM AG
PSHM BL
PSHM BH
PSHM BG
PSHM AR1
PSHM AR2
PSHM AR3
PSHM T
pshm brc
pshm rsa
pshm rea
STM #num1, AR3
STM #num2, AR4
STM #result, AR5
ADD *AR3, *AR4, A
STH A, *AR5
STM #08h, HPIC ; Interrupt
STM #0FFFFh, IFR
ST #1,*(_flag)
popm rea
popm rsa
popm brc
POPM T
POPM AR3
POPM AR2
POPM AR1
POPM BG
POPM BH
POPM BL
POPM AG
POPM AH
POPM AL
POPM ST1
POPM ST0
RETE
;***********************************************
;* C5409 serial port registers *
;*************** MCBSP0 ************************
DRR10 .set 21H ; Data Receive Register
DXR10 .set 23H ; Data Transmit Register
SPSA0 .set 0038H ; Serial Port 0 Sub-bank Address Register
SPSD0 .set 0039H ; Serial Port 0 Sub-bank Data Register
drr11 .set 41H ; Data Receive Register
dxr11 .set 43H ; Data Transmit Register
SPSA1 .set 0048H ; Serial Port 1 Sub-bank Address Register
SPSD1 .set 0049H ; Serial Port 1 Sub-bank Data Register
;*----------- MCBSP CONTROL REGS --------------*
SPCR1_SUBADDR .set 0000H ; Serial Port Control Register 1 (subaddress)
SPCR2_SUBADDR .set 0001H ; Serial Port 1 Control Register 2 (subaddress)
RCR1_SUBADDR .set 0002H ; Receive Control Register 1 (subaddress)
RCR2_SUBADDR .set 0003H ; Receive Control Register 2 (subaddress)
XCR1_SUBADDR .set 0004H ; Transmit Control Register 1 (subaddress)
XCR2_SUBADDR .set 0005H ; Transmit Control Register 2 (subaddress)
SRGR1_SUBADDR .set 0006H ; Sample Rate Genarator Register 1 (subaddress)
SRGR2_SUBADDR .set 0007H ; Sample Rate Genarator Register 2 (subaddress)
PCR_SUBADDR .set 000EH ; Pin Control Register (subaddress)
;*-----------SPCR1 register organization -------------*
;*-------------------------------------------------------------------------*
;*| 15 | 14 13| 12 11 | 10 8 | 7 | 6 |5 4| 3 | 2 | 1 | 0 |*
;*-------------------------------------------------------------------------*
;*| DLB | RJUST |CLKSTP | RES |DXENA|ABIS|RINTM|RSYNCERR|RFULL|RRDY|RRST|*
;*-------------------------------------------------------------------------*
K_DLB .set 0b<<15
K_RJUST .set 00b<<13
K_CLKSTP .set 00b<<11
K_SPCR1_RES .set 000b<<8
K_DXENA .set 1b<<7
K_ABIS .set 0b<<6
K_RINTM .set 10b<<4
K_RSYNCERR .set 0b<<3
K_RFULL .set 0b<<2
K_RRDY .set 0b<<1
K_RRST .set 1b
K_SPCR1 .set K_DLB|K_RJUST|K_CLKSTP|K_SPCR1_RES|K_DXENA|K_ABIS|K_RINTM|K_RSYNCERR|K_RFULL|K_RRDY|K_RRST
;*-----------SPCR2 register organization -------------*
;*--------------------------------------------------------------*
;*| 15 10 | 9 | 8 | 7 | 6 | 5 4 | 3 | 2 | 1 | 0 |*
;*--------------------------------------------------------------*
;*| RES |FREE|SOFT|FRST|GRST|XINTM|XSYNCERR|XEMPTY|XRDY|XRST |*
;*--------------------------------------------------------------*
K_SPCR2_RES .set 000000b<<10
K_FREE .set 0b<<9
K_SOFT .set 0b<<8
K_FRST .set 1b<<7
K_GRST .set 1b<<6
K_XINTM .set 10b<<4
K_SYNCERR .set 0b<<3
K_XEMPTY .set 0b<<2
K_XRDY .set 0b<<1
K_XRST .set 1b
K_SPCR2 .set K_SPCR2_RES|K_FREE|K_SOFT|K_FRST|K_GRST|K_XINTM|K_SYNCERR|K_XEMPTY|K_XRDY|K_XRST
;*-----------PCR register organization -------------*
;*---------------------------------------------------------------------------------------------*
;*|15 14| 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 1*
;*---------------------------------------------------------------------------------------------*
;*| RES |XIOEN|RIOEN|FSXM|FRSM|CLKXM|CLKRM|RES|CLKS_STAT|DX_STAT|DR_STAT|FSXP|FSRP|CLKXP|CLXRP|*
;*---------------------------------------------------------------------------------------------*
K_PCR_RES .set 00b<<14
K_XIOEN .set 0b<<13
K_RIOEN .set 0b<<12
K_FSXM .set 1b<<11
K_FRSM .set 0b<<10
K_CLKXM .set 1b<<9
K_CLKRM .set 0b<<8
K_PCR_RES1 .set 0b<<8
K_CLKS_STAT .set 0b<<6
K_DX_STAT .set 0b<<5
K_DR_STAT .set 0b<<4
K_FSXP .set 0b<<3
K_FSRP .set 0b<<2
K_CLKXP .set 0b<<1
K_CLKRP .set 0b
K_PCR .set K_PCR_RES1|K_XIOEN|K_RIOEN|K_FSXM|K_FRSM|K_CLKXM|K_CLKRM|K_PCR_RES|K_CLKS_STAT|K_DX_STAT|K_DR_STAT|K_FSXP|K_FSRP|K_CLKXP|K_CLKRP
;*-----------RCR1 register organization -------------*
;*----------------------------------*
;*| 15 | 14 8 | 7 5 | 4 0 |*
;*----------------------------------*
;*| RES | RFRLEN1 | RWDLEN1 | RES |*
;*----------------------------------*
K_RCR1_RES .set 0b<<15
K_RFRLEN1 .set 0000000b<<8
K_RWDLEN1 .set 000b<<5
K_RCR1_RES1 .set 00000b
K_RCR1 .set K_RCR1_RES|K_RCR1_RES1|K_RFRLEN1|K_RWDLEN1
;*-----------RCR2 register organization -------------*
;*----------------------------------------------------*
;*| 15 | 14 8 | 7 5 | 4 3 | 2 | 1 0 |*
;*----------------------------------------------------*
;*| RPHASE | RFRLEN2 | RWDLEN2 |RCOMPAND|RFIG|RDATDLY|*
;*----------------------------------------------------*
K_RPHASE .set 0b<<15
K_RFRLEN2 .set 0000000b<<8
K_RWDLEN2 .set 000b<<5
K_RCOMPAND .set 10b<<3
K_RFIG .set 0b<<2
K_RDATDLY .set 01b
K_RCR2 .set K_RPHASE|K_RDATDLY|K_RFRLEN2|K_RWDLEN2|K_RCOMPAND|K_RFIG
;*-----------XCR1 register organization -------------*
;*----------------------------------*
;*| 15 | 14 8 | 7 5 | 4 0 |*
;*----------------------------------*
;*| RES | XFRLEN1 | XWDLEN1 | RES |*
;*----------------------------------*
K_XCR1_RES .set 0b<<15
K_XFRLEN1 .set 0000000b<<8
K_XWDLEN1 .set 000b<<5
K_XCR1_RES1 .set 00000b
K_XCR1 .set K_XCR1_RES|K_XCR1_RES1|K_XFRLEN1|K_XWDLEN1
;*-----------XCR2 register organization -------------*
;*----------------------------------------------------*
;*| 15 | 14 8 | 7 5 | 4 3 | 2 | 1 0 |*
;*----------------------------------------------------*
;*| XPHASE | XFRLEN2 | XWDLEN2 |XCOMPAND|XFIG|XDATDLY|*
;*----------------------------------------------------*
K_XPHASE .set 0b<<15
K_XFRLEN2 .set 0000000b<<8
K_XWDLEN2 .set 000b<<5
K_XCOMPAND .set 10b<<3
K_XFIG .set 0b<<2
K_XDATDLY .set 01b
K_XCR2 .set K_XPHASE|K_XDATDLY|K_XFRLEN2|K_XWDLEN2|K_XCOMPAND|K_XFIG
;*------------Sample Rate Generate Register 1-------------*
;*--------------------------------------------------------*
;*|15 8|7 0|*
;*--------------------------------------------------------*
;*| FWID | CLKGTDV |*
;*--------------------------------------------------------*
K_FWID .SET 00000000b << 8
K_CLKGDV .SET 00110001b << 0
K_SRGR1 .SET K_FWID|K_CLKGDV
;*------------Sample Rate Generate Register 2-------------*
;*--------------------------------------------------------*
;*| 15 | 14 | 13 | 12 | 11 0|*
;*--------------------------------------------------------*
;*|GSYNC|CLKSP|CLKSM|FSGM| FPER |*
;*--------------------------------------------------------*
K_GSYNC .SET 1b << 15
K_CLKSP .SET 1b << 14
K_CLKSM .SET 1b << 13
K_FSGM .SET 1b << 12
K_FPER .SET 000011111001b
K_SRGR2 .SET K_GSYNC|K_CLKSP|K_CLKSM|K_FSGM|K_FPER
;*------------PMST register organization---------------------*
;*------------------------------------------------------------*
;*| 15 7 | 6 | 5 | 4 | 3 | 2 | 1 0 |*
;*------------------------------------------------------------*
;*| IPTR | MP/MC- | OVLY | AVIS | DROM | CLKOFF | RESEVED |*
;*------------------------------------------------------------*
K_IPTR .SET 011111110b << 07 ; 111111111b at reset
K_MP_MC .SET 1b << 6 ; 1 at reset
K_OVLY .SET 1b << 5 ; 0 at reset
K_AVIS .SET 0b << 4 ; 0 at reset
K_DROM .SET 0b << 3 ; 0 at reset
K_CLKOFF .SET 0b << 2 ; 0 at reset
K_PMST_RESR .SET 00b ; 00b at reset
K_PMST .SET K_IPTR|K_OVLY|K_DROM|K_CLKOFF|K_PMST_RESR
;*----------------SWWSR register organization-------------------*
;*--------------------------------------------------------------*
;*| 15 | 14 12| 11 9| 8 6 | 5 3| 2 0|*
;*--------------------------------------------------------------*
;*| reserved | I/O | DATA | DATA | PROGRAM | PROGRAM |*
;*--------------------------------------------------------------*
K_SWWSR_RESV .SET 0b << 15 ; reset
K_IO .SET 000b << 12 ; reset
K_DATA1 .SET 000b << 9 ; reset
K_DATA2 .SET 000b << 6 ; reset
K_PROGRAM1 .SET 000b << 3 ; reset
K_PROGRAM2 .SET 000b ; reset
K_SWWSR .SET K_SWWSR_RESV|K_IO|K_DATA1|K_DATA2|K_PROGRAM1|K_PROGRAM2
;*Bank Switch Control Register(BSCR) organization*
;*----------------------------------------*
;*| 15 12| 11 | 10 2 | 1 | 0 |*
;*----------------------------------------*
;*| BNKCMP | PS-DS | Reserved | BH | EXIO|*
;*----------------------------------------*
K_BNKCMP .SET 1111b << 12 ; bank size = 64k
K_PSDS .SET 0b << 11 ; reset
K_BSCR_RESV .SET 000000000b << 2
K_BH .SET 0b << 1 ; reset
K_EXIO .SET 0b ; reset
K_BSCR .SET K_BNKCMP|K_PSDS|K_BSCR_RESV|K_BH|K_EXIO
;*--------------CLKMD register organization---------------*
;*--------------------------------------------------------*
;*| 15 12 | 11 | 10 3| 2 | 1 | 0 |*
;*--------------------------------------------------------*
;*| PLLMUL | PLLDIV |PLLCOUNT|PLLON/OFF|PLLNDIV|PLLSTATUS|*
;*--------------------------------------------------------*
K_PLLMUL .SET 1001b<<12
K_PLLDIV .SET 0b<<11
K_PLLCOUNT .SET 00000000b<<3
K_PLLON_OFF .SET 1b<<2
K_PLLNDIV .SET 1b<<1
K_PLLSTATUS .SET 1b
K_CLKMD .SET K_PLLMUL|K_PLLDIV|K_PLLCOUNT|K_PLLON_OFF|K_PLLNDIV|K_PLLSTATUS
_init_54:
STM #K_PMST ,PMST
STM #K_SWWSR,SWWSR
STM #K_BSCR,BSCR
NOP
NOP
NOP
STM #0,CLKMD
NOP
NOP
STM #K_CLKMD,CLKMD
STM #0, IMR
NOP
NOP
NOP
NOP
STM #0FFFFh, IFR ;
STM #0200h, IMR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RET
; Interupt Mask Regiser(IMR) Register
;*------------------------------------------------------------------------------------------------------------
;*|15 14| 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
;*------------------------------------------------------------------------------------------------------------
;*|resvd|DMAC5|DMAC4|BXINT1/DMAC3|BRINT1/DMAC2|HPINT|INT3|TINT1/DMAC1|DMAC0|BXINT0|BRINT0|TINT|INT2|INT1|INT0|
;*------------------------------------------------------------------------------------------------------------
K_IMR_BXINT0 .SET 1b << 5 ; enable McBSP TRANSMIT
K_IMR_BRINT0 .SET 1b << 4 ; enable McBSP receive
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