LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY ADC0809 IS       --實(shí)體名為ADC0809
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);  --IN 8位輸入數(shù)據(jù)信號(hào)
CLK,EOC:IN STD_LOGIC;         --CLK 輸入時(shí)鐘和EOC 轉(zhuǎn)換結(jié)束信號(hào)
ALE,START,OE,ADDA:OUT STD_LOGIC; --ALE鎖存信號(hào)，START啟動(dòng)信號(hào)
-- OE 	輸出容許，ADDA  
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));---Q輸出數(shù)據(jù) 
END ADC0809; 

ARCHITECTURE ARC OF ADC0809 IS     --結(jié)構(gòu)體說(shuō)明
TYPE states IS(st0,st1,st2,st3,st4,st5,st6,st7);-- 定義狀態(tài)量 
SIGNAL current_state,next_state:states:=st0; -- 狀態(tài)初始化
SIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0);  --狀態(tài)寄存 
SIGNAL LOCK:STD_LOGIC;  --數(shù)據(jù)鎖存信號(hào)

BEGIN 
   ADDA<='1'; 
A：   PROCESS(current_state,EOC) BEGIN   -- 進(jìn)程開(kāi)始該進(jìn)程完成AD轉(zhuǎn)換的8個(gè)                                         --過(guò)程，可對(duì)照AD0809的時(shí)序圖
CASE current_state IS 
WHEN st0=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<= st1; 
   -- 初始狀態(tài)
WHEN st1=>ALE<='1';START<='0';OE<='0';LOCK<='0';next_state<= st2; 
  --ALE =1 選擇通道
WHEN st2=>ALE<='0';START<='1';OE<='0';LOCK<='0';next_state<= st3; 
   --啟動(dòng)AD 
WHEN st3=>ALE<='0';START<='0';OE<='0';LOCK<='0'; 
IF(EOC='1')THEN next_state<=st3; 
  --等待轉(zhuǎn)換結(jié)開(kāi)始
ELSE next_state<=st4; 
END IF; 
WHEN st4=>ALE<='0';START<='0';OE<='0';LOCK<='0'; 
IF(EOC='0')THEN next_state<=st4;
   --等待轉(zhuǎn)換結(jié)束 
ELSE next_state<=st5; 
END IF; 
WHEN st5=>ALE<='0';START<='0';OE<='1';LOCK<='0';next_state<= st6; 
-- 設(shè)置輸出AD使能
WHEN st6=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<= st7; 
--LOCK=1，使能轉(zhuǎn)換數(shù)據(jù)輸出  
WHEN st7=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<= st0; 
-- 新的循環(huán)開(kāi)始
WHEN OTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<= st0; 
-- 容錯(cuò)處理
END CASE; 
END PROCESS; 

B ：PROCESS(CLK)   -- 更新?tīng)顟B(tài) BUT 時(shí)鐘頻率？？？
BEGIN 
IF(CLK'EVENT AND CLK='1') THEN 
current_state<=next_state; 
END IF; 
END PROCESS; 

C：PROCESS(CLK) 
BEGIN 
IF(CLK'EVENT AND CLK='1') THEN 
IF LOCK='1'THEN    --當(dāng)鎖存有效時(shí)輸入數(shù)據(jù)
REG<=D; 
END IF; 
END IF;
END PROCESS;

Q<=REG;   -- 數(shù)據(jù)輸出
END ARC;