?? initport.c
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/*
*********************************************************************************************************
* 文件: InitPort.C
* 描述: 初始化 Port.
* 編寫(xiě): kaka (sn.kaka@yahoo.com).In Hisense
*********************************************************************************************************
*/
#include "44b0x.h"
void InitPort (void)
{
// * Port of Group A Control Registers *.
#define PA9 0 // 0 = Output 1 = ADDR24
#define PA8 1 // 0 = Output 1 = ADDR23
#define PA7 1 // 0 = Output 1 = ADDR22
#define PA6 1 // 0 = Output 1 = ADDR21
#define PA5 1 // 0 = Output 1 = ADDR20
#define PA4 1 // 0 = Output 1 = ADDR19
#define PA3 1 // 0 = Output 1 = ADDR18
#define PA2 1 // 0 = Output 1 = ADDR17
#define PA1 1 // 0 = Output 1 = ADDR16
#define PA0 1 // 0 = Output 1 = ADDR0
PCONA = ((PA9<<9)+(PA8<<8)+(PA7<<7)+(PA6<<6)+(PA5<<5)+(PA4<<4)+(PA3<<3)+(PA2<<2)+(PA1<<1)+PA0);
PDATA = 0x1ff;
// * Port of Group B Control Registers *.
#define PB10 1 // 0 = Output 1 = nGCS5
#define PB9 1 // 0 = Output 1 = nGCS4
#define PB8 1 // 0 = Output 1 = nGCS3
#define PB7 1 // 0 = Output 1 = nGCS2
#define PB6 1 // 0 = Output 1 = nGCS1
#define PB5 1 // 0 = Output 1 = nWBE3/nBE3/DQM3
#define PB4 1 // 0 = Output 1 = nWBE2/nBE2/DQM2
#define PB3 1 // 0 = Output 1 = nSRAS/nCAS3
#define PB2 1 // 0 = Output 1 = nSCAS/nCAS2
#define PB1 1 // 0 = Output 1 = SCLK
#define PB0 1 // 0 = Output 1 = SCKE
PCONB = ((PB10<<10)+(PB9<<9)+(PB8<<8)+(PB7<<7)+(PB6<<6)+(PB5<<5)+(PB4<<4)+(PB3<<3)+(PB2<<2)+(PB1<<1)+PB0);
PDATB = 0x7ff;
// * Port of Group C Control Registers *.
#define PC15 1 // 00 = Input 01 = Output 10 = DATA31 11 = nCTS0
#define PC14 1 // 00 = Input 01 = Output 10 = DATA30 11 = nRTS0
#define PC13 3 // 00 = Input 01 = Output 10 = DATA29 11 = RxD1
#define PC12 3 // 00 = Input 01 = Output 10 = DATA28 11 = TxD1
#define PC11 3 // 00 = Input 01 = Output 10 = DATA27 11 = nCTS1
#define PC10 3 // 00 = Input 01 = Output 10 = DATA26 11 = nRTS1
#define PC9 1 // 00 = Input 01 = Output 10 = DATA25 11 = nXDREQ1
#define PC8 1 // 00 = Input 01 = Output 10 = DATA24 11 = nXDACK1
#define PC7 3 // 00 = Input 01 = Output 10 = DATA23 11 = VD4
#define PC6 3 // 00 = Input 01 = Output 10 = DATA22 11 = VD5
#define PC5 3 // 00 = Input 01 = Output 10 = DATA21 11 = VD6
#define PC4 3 // 00 = Input 01 = Output 10 = DATA20 11 = VD7
#define PC3 1 // 00 = Input 01 = Output 10 = DATA19 11 = IISCLK
#define PC2 1 // 00 = Input 01 = Output 10 = DATA18 11 = IISDI
#define PC1 1 // 00 = Input 01 = Output 10 = DATA17 11 = IISDO
#define PC0 1 // 00 = Input 01 = Output 10 = DATA16 11 = IISLRCK
PCONC = ((PC15<<30)+(PC14<<28)+(PC13<<26)+(PC12<<24)+(PC11<<22)+(PC10<<20)+(PC9<<18)+(PC8<<16)+(PC7<<14)+(PC6<<12)+(PC5<<10)+(PC4<<8)+(PC3<<6)+(PC2<<4)+(PC1<<2)+PC0);
PDATC = 0x0ffff; // All I/O Is High
PUPC = ~0x0ff00; // PULL UP RESISTOR should be enabled to I/O
// Port of Group D Control Registers.
#define PD7 1 // 00 = Input 01 = Output 10 = VFRAME 11 = Reserved
#define PD6 1 // 00 = Input 01 = Output 10 = VM 11 = Reserved
#define PD5 1 // 00 = Input 01 = Output 10 = VLINE 11 = Reserved
#define PD4 1 // 00 = Input 01 = Output 10 = VCLK 11 = Reserved
#define PD3 1 // 00 = Input 01 = Output 10 = VD3 11 = Reserved
#define PD2 1 // 00 = Input 01 = Output 10 = VD2 11 = Reserved
#define PD1 1 // 00 = Input 01 = Output 10 = VD1 11 = Reserved
#define PD0 1 // 00 = Input 01 = Output 10 = VD0 11 = Reserved
PCOND = ((PD7<<14)+(PD6<<12)+(PD5<<10)+(PD4<<8)+(PD3<<6)+(PD2<<4)+(PD1<<2)+PD0);
PDATD = 0x0ff;
PUPD = 0x0;
// Port of Group E Control Registers.
#define PE8 2 // 00 = Reserved(ENDIAN) 01 = Output 10 = CODECLK 11 = Reserved
#define PE7 1 // 00 = Input 01 = Output 10 = TOUT4 11 = VD7
#define PE6 1 // 00 = Input 01 = Output 10 = TOUT3 11 = VD6
#define PE5 1 // 00 = Input 01 = Output 10 = TOUT2 11 = TCLK in
#define PE4 1 // 00 = Input 01 = Output 10 = TOUT1 11 = TCLK in
#define PE3 0 // 00 = Input 01 = Output 10 = TOUT0 11 = Reserved
#define PE2 2 // 00 = Input 01 = Output 10 = RxD0 11 = Reserved
#define PE1 2 // 00 = Input 01 = Output 10 = TxD0 11 = Reserved
#define PE0 1 // 00 = Input 01 = Output 10 = Fpllo out 11 = Fout out
PCONE = ((PE8<<16)+(PE7<<14)+(PE6<<12)+(PE5<<10)+(PE4<<8)+(PE3<<6)+(PE2<<4)+(PE1<<2)+PE0);
PDATE = 0x1ff; // All I/O Is High
PUPE = 0x06; // PE8 do not have programmable pull-up resistor.
// Port of Group F Control Registers.
#define PF8 1 //4 // 000 = Input 001 = Output 010 = nCTS1 011 = SIOCLK 100 = IISCLK Others = Reserved
#define PF7 1 //1 // 000 = Input 001 = Output 010 = RxD1 011 = SIORxD 100 = IISDI Others = Reserved
#define PF6 1 //4 // 000 = Input 001 = Output 010 = TxD1 011 = SIORDY 100 = IISDO Others = Reserved
#define PF5 1 //4 // 000 = Input 001 = Output 010 = nRTS1 011 = SIOTxD 100 = IISLRCK Others = Reserved
#define PF4 1 //1 // 00 = Input 01 = Output 10 = nXBREQ 11 = nXDREQ0
#define PF3 1 //1 // 00 = Input 01 = Output 10 = nXBACK 11 = nXDACK0
#define PF2 1 //1 // 00 = Input 01 = Output 10 = nWAIT 11 = Reserved
#define PF1 1 //2 // 00 = Input 01 = Output 10 = IICSDA 11 = Reserved
#define PF0 1 //2 // 00 = Input 01 = Output 10 = IICSCL 11 = Reserved
PCONF = ((PF8<<19)+(PF7<<16)+(PF6<<13)+(PF5<<10)+(PF4<<8)+(PF3<<6)+(PF2<<4)+(PF1<<2)+PF0);
PDATF = 0x1ff; // All I/O Is High
PUPF = 0x163;
// Port of Group G Control Registers.
#define PG7 3 // 00 = Input 01 = Output 10 = IISLRCK 11 = EINT7
#define PG6 3 // 00 = Input 01 = Output 10 = IISDO 11 = EINT6
#define PG5 3 // 00 = Input 01 = Output 10 = IISDI 11 = EINT5
#define PG4 3 // 00 = Input 01 = Output 10 = IISCLK 11 = EINT4
#define PG3 3 // 00 = Input 01 = Output 10 = nRTS0 11 = EINT3
#define PG2 3 // 00 = Input 01 = Output 10 = nCTS0 11 = EINT2
#define PG1 3 // 00 = Input 01 = Output 10 = VD5 11 = EINT1
#define PG0 3 // 00 = Input 01 = Output 10 = VD4 11 = EINT0
PCONG = ((PG7<<14)+(PG6<<12)+(PG5<<10)+(PG4<<8)+(PG3<<6)+(PG2<<4)+(PG1<<2)+PG0);
PDATG = 0x0ff;
PUPG = 0x00; // should be enabled
// Pull-up Control Register.
#define HZSTOP 1 // 0 = Previous state of PAD 1 = HZ @ stop
#define SPUCR1 0 // 0 = DATA[15:8] port pull-up resistor is enabled 1 = DATA[15:8] port pull-up resistor is disabled
#define SPUCR0 0 // 0 = DATA[7:0] port pull-up resistor is enabled 1 = DATA[7:0] port pull-up resistor is disabled
SPUCR = ((HZSTOP<<2)+(SPUCR1<<1)+SPUCR0);
// External Interrupt Control Register
#define EINT7 0 // 000 = Low level interrupt 001 = High level interrupt
// 01x = Falling edge triggered 10x = Rising edge triggered
// 11x = Both edge triggered
#define EINT6 0 // ...
#define EINT5 0 // ...
#define EINT4 0 // ...
#define EINT3 0 // ...
#define EINT2 0 // ...
#define EINT1 0 // ... 高電平中斷.!!
#define EINT0 0 // ...
EXTINT = ((EINT7<<28)+(EINT6<<24)+(EINT5<<20)+(EINT4<<14)+(EINT3<<12)+(EINT2<<8)+(EINT1<<4)+EINT0);
}
/*
*********************************************************************************************************
* END
*********************************************************************************************************
*/
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