?? _primary.vhd
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library verilog;use verilog.vl_types.all;entity PSR_Fresh is port( in_CPSR_StatusRegisters: in vl_logic_vector(31 downto 0); in_CPSR_ALUShell: in vl_logic_vector(31 downto 0); in_ALUWriteEnable: in vl_logic; in_CPSR_MEM : in vl_logic_vector(31 downto 0); in_MEMWriteEnable: in vl_logic; out_CPSR_Fresh : out vl_logic_vector(31 downto 0); out_IsInPrivilegedMode: out vl_logic );end PSR_Fresh;
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