library verilog;use verilog.vl_types.all;entity CanGoGen is    port(        out_IFCanGo     : out    vl_logic;        out_IDCanGo     : out    vl_logic;        out_EXECanGo    : out    vl_logic;        out_MEMCanGo    : out    vl_logic;        in_IFOwnCanGo   : in     vl_logic;        in_IDOwnCanGo   : in     vl_logic;        in_EXEOwnCanGo  : in     vl_logic;        in_MEMOwnCanGo  : in     vl_logic    );end CanGoGen;