/* pentiumLib.c - Pentium and Pentium[234] library *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01f,20nov01,hdn  doc clean up for 5.501e,01nov01,hdn  added pentiumMsrInit() and pentiumMcaEnable().01d,21aug01,hdn  added P5/P6 PMC routines from T31 ver 01e		 fixed a bug in pentiumMtrr[GS]et() (spr 68103)01c,24mar99,jdi  doc: added basic formatting cmds, particularly .CS/.CE		 to set off code snippets as per standard practice.01b,17apr98,hdn  fixed typo.01b,17apr98,hdn  added documentation.01a,09jul97,hdn  written.*//*DESCRIPTIONThis library provides Pentium and Pentium[234] specific routines. .SS "MTRR (Memory Type Range Register)"MTRR (Memory Type Range Register) are a new feature introduced in the P6 family processor that allow the processor to optimize memory operationsfor different types of memory, such as RAM, ROM, frame buffer memory, andmemory-mapped IO.  MTRRs configure an internal map of how physical address ranges are mapped to various types of memory.  The processor uses this internalmap to determine the cacheability of various physical memory locations and theoptimal method of accessing memory locations.  For example, if a memorylocation is specified in an MTRR as write-through memory, the processor handlesaccesses to this location as follows.  It reads data from that location in lines and caches the read data or maps all writes to that location to the busand updates the cache to maintain cache coherency.  In mapping the physicaladdress space with MTRRs, the processor recognizes five types of memory:uncacheable (UC), write-combining (WC), write-through (WT),write-protected (WP), and write-back (WB).There is one table - sysMtrr[] in sysLib.c - and four routines to interfacethe MTRR.  These four routines are:.CS  void pentiumMtrrEnable (void)  void pentiumMtrrDisable (void)  STATUS pentiumMtrrGet      (      MTRR * pMtrr		/@ MTRR table @/      )  STATUS pentiumMtrrSet (void)      (      MTRR * pMtrr		/@ MTRR table @/      ).CEpentiumMtrrEnable() enables MTRR, pentiumMtrrDisable() disables MTRR.pentiumMtrrGet() gets MTRRs to the specified MTRR table.pentiumMtrrGet() sets MTRRs from the specified MTRR table.The MTRR table is defined as follows:.CStypedef struct mtrr_fix         /@ MTRR - fixed range register @/    {    char type[8];		/@ address range: [0]=0-7 ... [7]=56-63 @/    } MTRR_FIX;typedef struct mtrr_var         /@ MTRR - variable range register @/    {    long long int base;		/@ base register @/    long long int mask;		/@ mask register @/    } MTRR_VAR;typedef struct mtrr             /@ MTRR @/    {    int cap[2];                 /@ MTRR cap register @/    int deftype[2];             /@ MTRR defType register @/    MTRR_FIX fix[11];           /@ MTRR fixed range registers @/    MTRR_VAR var[8];            /@ MTRR variable range registers @/    } MTRR;.CEFixed Range Register's type array can be one of following memory types.MTRR_UC (uncacheable), MTRR_WC (write-combining), MTRR_WT (write-through), MTRR_WP (write-protected), and MTRR_WB (write-back).MTRR is enabled in sysHwInit()..SS "PMC (Performance Monitoring Counters)"The P5 and P6 family of processors has two performance-monitoring countersfor use in monitoring internal hardware operations. These counters areduration or event counters that can be programmed to count any of approximately100 different types of events, such as the number of instructions decoded,number of interrupts received, or number of cache loads. However, the set ofevents can be counted with PMC is different in the P5 and P6 family ofprocessors; and the locations and bit difinitions of the related counter andcontrol registers are also different. So there are two set of PMC routines,one for P6 family and one for P5 family respectively in pentiumALib. Forconvenience, the PMC routines here are acting as wrappers to those routinesin pentiumALib. They will call the P5 or P6 routine depending on the processor type.There are twelve routines to interface the PMC.  These twelve routines are:.CS  STATUS pentiumPmcStart         (         int pmcEvtSel0;        /@ performance event select register 0 @/         int pmcEvtSel1;        /@ performance event select register 1 @/         )  STATUS pentiumPmcStart0         (         int pmcEvtSel0;        /@ performance event select register 0 @/         )  STATUS pentiumPmcStart1         (         int pmcEvtSel1;        /@ performance event select register 1 @/         )  void   pentiumPmcStop (void)  void   pentiumPmcStop0 (void)  void   pentiumPmcStop1 (void)  void   pentiumPmcGet         (         long long int * pPmc0; /@ performance monitoring counter 0 @/         long long int * pPmc1; /@ performance monitoring counter 1 @/         )  void   pentiumPmcGet0         (         long long int * pPmc0; /@ performance monitoring counter 0 @/         )  void   pentiumPmcGet1         (         long long int * pPmc1; /@ performance monitoring counter 1 @/         )  void   pentiumPmcReset (void)  void   pentiumPmcReset0 (void)  void   pentiumPmcReset1 (void).CEpentiumPmcStart() starts both PMC0 and PMC1. pentiumPmcStart0() starts PMC0,and pentiumPmcStart1() starts PMC1.pentiumPmcStop() stops both PMC0 and PMC1. pentiumPmcStop0() stops PMC0, and pentiumPmcStop1() stops PMC1.pentiumPmcGet() gets contents of PMC0 and PMC1.  pentiumPmcGet0() getscontents of PMC0, and pentiumPmcGet1() gets contents of PMC1.pentiumPmcReset() resets both PMC0 and PMC1.  pentiumPmcReset0() resetsPMC0, and pentiumPmcReset1() resets PMC1.PMC is enabled in sysHwInit().  Selected events in the default configurationare PMC0 = number of hardware interrupts received and PMC1 = number ofmisaligned data memory references..SS "MSR (Model Specific Registers)"The P5(Pentium), P6(PentiumPro, II, III), and P7(Pentium4) family processorscontain a model-specific registers (MSRs).  These registers are implement-ation specific.  They are provided to control a variety of hardware and software related features including the performance monitoring, the debugextensions, the machine check architecture, etc.There is one routine - pentiumMsrInit() - to initialize all the MSRs.This routine initializes all the MSRs in the processor and works on eitherP5, P6 or P7 family processors..SS "MCA (Machine Check Architecture)"The P5(Pentium), P6(PentiumPro, II, III), and P7(Pentium4) family processorshave a machine-check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as system bus errors, ECCerrors, parity errors, cache errors and TLB errors.  It consists of a setof model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs for recording errors that are detected.The processor signals the detection of a machine-check error by generatinga machine-check exception, which an abort class exception.  The implement-ation of the machine-check architecture, does not ordinarily permit the processor to be restarted reliably after generating a machine-check exception.  However, the machine-check exception handler can collectinformation about the machine-check error from the machine-check MSRs.There is one routine - pentiumMcaEnable() - to enable or disable the MCA.The routine enables or disables 1) the Machine Check Architecture and its Error Reporting register banks 2) the Machine Check Exception by togglingthe MCE bit in the CR4.  This routine works on either P5, P6 or P7 family.SEE ALSO:.I PentiumALib, "Pentium, Pentium[234] Family Developer's Manual"*//* includes */#include "vxWorks.h"#include "regs.h"#include "arch/i86/pentiumLib.h"#include "vxLib.h"#include "intLib.h"#include "cacheLib.h"/* defines */#define	IA32_MISC_ENABLE_DEFAULT	(MSC_FAST_STRING_ENABLE | \					 MSC_THERMAL_MON_ENABLE)#define MSR_ROB_CR_BKUPTMPDR6_DEFAULT	0x4/* externals */IMPORT CPUID sysCpuId;IMPORT int sysProcessor;/* globals */PENTIUM_MSR pentiumMsrP5[] = {    {MSR_P5_MC_ADDR,		"P5_MC_ADDR"},    {MSR_P5_MC_TYPE,		"P5_MC_TYPE"},    {MSR_TSC,			"TSC"},    {MSR_CESR,			"CESR"},    {MSR_CTR0,			"CTR0"},    {MSR_CTR1,			"CTR1"},    };INT32 pentiumMsrP5NumEnt = NELEMENTS (pentiumMsrP5);PENTIUM_MSR pentiumMsrP6[] = {    {MSR_P5_MC_ADDR,		"P5_MC_ADDR"},    {MSR_P5_MC_TYPE,		"P5_MC_TYPE"},    {MSR_TSC,			"TSC"},    {IA32_PLATFORM_ID,		"IA32_PLATFORM_ID"},    {MSR_APICBASE,		"APICBASE"},    {MSR_EBL_CR_POWERON,	"EBL_CR_POWERON"},    {MSR_TEST_CTL,		"TEST_CTL"},    /* RW triggers the loading of the microcode update.    {MSR_BIOS_UPDT_TRIG,	"BIOS_UPDT_TRIG"},    */    {MSR_BBL_CR_D0,		"BBL_CR_D0"},    {MSR_BBL_CR_D1,		"BBL_CR_D1"},    {MSR_BBL_CR_D2,		"BBL_CR_D2"},    {MSR_BIOS_SIGN,		"BIOS_SIGN"},    {MSR_PERFCTR0,		"PERFCTR0"},    {MSR_PERFCTR1,		"PERFCTR1"},    {MSR_MTRR_CAP,		"MTRR_CAP"},    {MSR_BBL_CR_ADDR,		"BBL_CR_ADDR"},    {MSR_BBL_CR_DECC,		"BBL_CR_DECC"},    {MSR_BBL_CR_CTL,		"BBL_CR_CTL"},    /* write only with Data=0, reading generates GPF exception.    {MSR_BBL_CR_TRIG,		"BBL_CR_TRIG"},    */    {MSR_BBL_CR_BUSY,		"BBL_CR_BUSY"},    {MSR_BBL_CR_CTL3,		"BBL_CR_CTL3"},    {MSR_SYSENTER_CS,		"SYSENTER_CS"},    {MSR_SYSENTER_ESP,		"SYSENTER_ESP"},    {MSR_SYSENTER_EIP,		"SYSENTER_EIP"},    {MSR_MCG_CAP,		"MCG_CAP"},    {MSR_MCG_STATUS,		"MCG_STATUS"},    /* generate GPF exception if not present.    {MSR_MCG_CTL,		"MCG_CTL"},    */    {MSR_EVNTSEL0,		"EVNTSEL0"},    {MSR_EVNTSEL1,		"EVNTSEL1"},    {MSR_DEBUGCTLMSR,		"DEBUGCTLMSR"},    {MSR_LASTBRANCH_FROMIP,	"LASTBRANCH_FROMIP"},    {MSR_LASTBRANCH_TOIP,	"LASTBRANCH_TOIP"},    {MSR_LASTINT_FROMIP,	"LASTINT_FROMIP"},    {MSR_LASTINT_TOIP,		"LASTINT_TOIP"},    {MSR_ROB_CR_BKUPTMPDR6,	"ROB_CR_BKUPTMPDR6"},    {MSR_MTRR_PHYS_BASE0,	"MTRR_PHYS_BASE0"},    {MSR_MTRR_PHYS_MASK0,	"MTRR_PHYS_MASK0"},    {MSR_MTRR_PHYS_BASE1,	"MTRR_PHYS_BASE1"},    {MSR_MTRR_PHYS_MASK1,	"MTRR_PHYS_MASK1"},    {MSR_MTRR_PHYS_BASE2,	"MTRR_PHYS_BASE2"},    {MSR_MTRR_PHYS_MASK2,	"MTRR_PHYS_MASK2"},    {MSR_MTRR_PHYS_BASE3,	"MTRR_PHYS_BASE3"},    {MSR_MTRR_PHYS_MASK3,	"MTRR_PHYS_MASK3"},    {MSR_MTRR_PHYS_BASE4,	"MTRR_PHYS_BASE4"},    {MSR_MTRR_PHYS_MASK4,	"MTRR_PHYS_MASK4"},    {MSR_MTRR_PHYS_BASE5,	"MTRR_PHYS_BASE5"},    {MSR_MTRR_PHYS_MASK5,	"MTRR_PHYS_MASK5"},    {MSR_MTRR_PHYS_BASE6,	"MTRR_PHYS_BASE6"},    {MSR_MTRR_PHYS_MASK6,	"MTRR_PHYS_MASK6"},    {MSR_MTRR_PHYS_BASE7,	"MTRR_PHYS_BASE7"},    {MSR_MTRR_PHYS_MASK7,	"MTRR_PHYS_MASK7"},    {MSR_MTRR_FIX_00000,	"MTRR_FIX_00000"},    {MSR_MTRR_FIX_80000,	"MTRR_FIX_80000"},    {MSR_MTRR_FIX_A0000,	"MTRR_FIX_A0000"},    {MSR_MTRR_FIX_C0000,	"MTRR_FIX_C0000"},    {MSR_MTRR_FIX_C8000,	"MTRR_FIX_C8000"},    {MSR_MTRR_FIX_D0000,	"MTRR_FIX_D0000"},    {MSR_MTRR_FIX_D8000,	"MTRR_FIX_D8000"},    {MSR_MTRR_FIX_E0000,	"MTRR_FIX_E0000"},    {MSR_MTRR_FIX_E8000,	"MTRR_FIX_E8000"},    {MSR_MTRR_FIX_F0000,	"MTRR_FIX_F0000"},    {MSR_MTRR_FIX_F8000,	"MTRR_FIX_F8000"},    {MSR_MTRR_DEFTYPE,		"MTRR_DEFTYPE"},    /* use pentiumMcaEnable() or pentiumMcaShow()    {MSR_MC0_CTL,		"MC0_CTL"},    {MSR_MC0_STATUS,		"MC0_STATUS"},    {MSR_MC0_ADDR,		"MC0_ADDR"},    {MSR_MC0_MISC,		"MC0_MISC"},    {MSR_MC1_CTL,		"MC1_CTL"},    {MSR_MC1_STATUS,		"MC1_STATUS"},    {MSR_MC1_ADDR,		"MC1_ADDR"},    {MSR_MC1_MISC,		"MC1_MISC"},    {MSR_MC2_CTL,		"MC2_CTL"},    {MSR_MC2_STATUS,		"MC2_STATUS"},    {MSR_MC2_ADDR,		"MC2_ADDR"},    {MSR_MC2_MISC,		"MC2_MISC"},    {MSR_MC4_CTL,		"MC4_CTL"},    {MSR_MC4_STATUS,		"MC4_STATUS"},    {MSR_MC4_ADDR,		"MC4_ADDR"},    {MSR_MC4_MISC,		"MC4_MISC"},    {MSR_MC3_CTL,		"MC3_CTL"},    {MSR_MC3_STATUS,		"MC3_STATUS"},    {MSR_MC3_ADDR,		"MC3_ADDR"},    {MSR_MC3_MISC,		"MC3_MISC"},    */    };INT32 pentiumMsrP6NumEnt = NELEMENTS (pentiumMsrP6);PENTIUM_MSR pentiumMsrP7[] = {    {IA32_P5_MC_ADDR,		"IA32_P5_MC_ADDR"},    {IA32_P5_MC_TYPE,		"IA32_P5_MC_TYPE"},    {IA32_TIME_STAMP_COUNTER,	"IA32_TIME_STAMP_COUNTER"},    {IA32_PLATFORM_ID,		"IA32_PLATFORM_ID"},    {IA32_APIC_BASE,		"IA32_APIC_BASE"},    {MSR_EBC_HARD_POWERON,	"EBC_HARD_POWERON"},    {MSR_EBC_SOFT_POWERON,	"EBC_SOFT_POWERON"},    {MSR_EBC_FREQUENCY_ID,	"EBC_FREQUENCY_ID"},    /* RW triggers the loading of the microcode update.    {IA32_BIOS_UPDT_TRIG,	"IA32_BIOS_UPDT_TRIG"},     */    {IA32_BIOS_SIGN_ID,		"IA32_BIOS_SIGN_ID"},    {IA32_MTRRCAP,		"IA32_MTRRCAP"},    {IA32_MISC_CTL,		"IA32_MISC_CTL"},    {IA32_SYSENTER_CS,		"IA32_SYSENTER_CS"},    {IA32_SYSENTER_ESP,		"IA32_SYSENTER_ESP"},    {IA32_SYSENTER_EIP,		"IA32_SYSENTER_EIP"},    {IA32_MCG_CAP,		"IA32_MCG_CAP"},    {IA32_MCG_STATUS,		"IA32_MCG_STATUS"},    /* generate GPF exception if not present.    {IA32_MCG_CTL,		"IA32_MCG_CTL"},    {IA32_MCG_EAX,		"IA32_MCG_EAX"},    {IA32_MCG_EBX,		"IA32_MCG_EBX"},    {IA32_MCG_ECX,		"IA32_MCG_ECX"},    {IA32_MCG_EDX,		"IA32_MCG_EDX"},    {IA32_MCG_ESI,		"IA32_MCG_ESI"},    {IA32_MCG_EDI,		"IA32_MCG_EDI"},    {IA32_MCG_EBP,		"IA32_MCG_EBP"},    {IA32_MCG_ESP,		"IA32_MCG_ESP"},    {IA32_MCG_EFLAGS,		"IA32_MCG_EFLAGS"},    {IA32_MCG_EIP,		"IA32_MCG_EIP"},    {IA32_MCG_MISC,		"IA32_MCG_MISC"},     */    {IA32_THERM_CONTROL,	"IA32_THERM_CONTROL"},    {IA32_THERM_INTERRUPT,	"IA32_THERM_INTERRUPT"},    {IA32_THERM_STATUS,		"IA32_THERM_STATUS"},    {IA32_MISC_ENABLE,		"IA32_MISC_ENABLE"},    {MSR_LER_FROM_LIP,		"LER_FROM_LIP"},    {MSR_LER_TO_LIP,		"LER_TO_LIP"},    {IA32_DEBUGCTL,		"IA32_DEBUGCTL"},    {MSR_LASTBRANCH_TOS,	"LASTBRANCH_TOS"},    {MSR_LASTBRANCH_0,		"LASTBRANCH_0"},    {MSR_LASTBRANCH_1,		"LASTBRANCH_1"},    {MSR_LASTBRANCH_2,		"LASTBRANCH_2"},    {MSR_LASTBRANCH_3,		"LASTBRANCH_3"},    {IA32_MTRR_PHYSBASE0,	"IA32_MTRR_PHYSBASE0"},    {IA32_MTRR_PHYSMASK0,	"IA32_MTRR_PHYSMASK0"},    {IA32_MTRR_PHYSBASE1,	"IA32_MTRR_PHYSBASE1"},    {IA32_MTRR_PHYSMASK1,	"IA32_MTRR_PHYSMASK1"},    {IA32_MTRR_PHYSBASE2,	"IA32_MTRR_PHYSBASE2"},    {IA32_MTRR_PHYSMASK2,	"IA32_MTRR_PHYSMASK2"},    {IA32_MTRR_PHYSBASE3,	"IA32_MTRR_PHYSBASE3"},    {IA32_MTRR_PHYSMASK3,	"IA32_MTRR_PHYSMASK3"},    {IA32_MTRR_PHYSBASE4,	"IA32_MTRR_PHYSBASE4"},    {IA32_MTRR_PHYSMASK4,	"IA32_MTRR_PHYSMASK4"},    {IA32_MTRR_PHYSBASE5,	"IA32_MTRR_PHYSBASE5"},    {IA32_MTRR_PHYSMASK5,	"IA32_MTRR_PHYSMASK5"},    {IA32_MTRR_PHYSBASE6,	"IA32_MTRR_PHYSBASE6"},    {IA32_MTRR_PHYSMASK6,	"IA32_MTRR_PHYSMASK6"},    {IA32_MTRR_PHYSBASE7,	"IA32_MTRR_PHYSBASE7"},    {IA32_MTRR_PHYSMASK7,	"IA32_MTRR_PHYSMASK7"},    {IA32_MTRR_FIX64K_00000,	"IA32_MTRR_FIX64K_00000"},    {IA32_MTRR_FIX16K_80000,	"IA32_MTRR_FIX16K_80000"},    {IA32_MTRR_FIX16K_A0000,	"IA32_MTRR_FIX16K_A0000"},    {IA32_MTRR_FIX4K_C0000,	"IA32_MTRR_FIX4K_C0000"},    {IA32_MTRR_FIX4K_C8000,	"IA32_MTRR_FIX4K_C8000"},    {IA32_MTRR_FIX4K_D0000,	"IA32_MTRR_FIX4K_D0000"},    {IA32_MTRR_FIX4K_D8000,	"IA32_MTRR_FIX4K_D8000"},    {IA32_MTRR_FIX4K_E0000,	"IA32_MTRR_FIX4K_E0000"},    {IA32_MTRR_FIX4K_E8000,	"IA32_MTRR_FIX4K_E8000"},    {IA32_MTRR_FIX4K_F8000,	"IA32_MTRR_FIX4K_F8000"},    {IA32_CR_PAT,		"IA32_CR_PAT"},    {IA32_MTRR_DEF_TYPE,	"IA32_MTRR_DEF_TYPE"},    {MSR_BPU_COUNTER0,		"BPU_COUNTER0"},    {MSR_BPU_COUNTER1,		"BPU_COUNTER1"},    {MSR_BPU_COUNTER2,		"BPU_COUNTER2"},    {MSR_BPU_COUNTER3,		"BPU_COUNTER3"},    {MSR_MS_COUNTER0,		"MS_COUNTER0"},    {MSR_MS_COUNTER1,		"MS_COUNTER1"},    {MSR_MS_COUNTER2,		"MS_COUNTER2"},    {MSR_MS_COUNTER3,		"MS_COUNTER3"},    {MSR_FLAME_COUNTER0,	"FLAME_COUNTER0"},    {MSR_FLAME_COUNTER1,	"FLAME_COUNTER1"},    {MSR_FLAME_COUNTER2,	"FLAME_COUNTER2"},    {MSR_FLAME_COUNTER3,	"FLAME_COUNTER3"},    {MSR_IQ_COUNTER0,		"IQ_COUNTER0"},    {MSR_IQ_COUNTER1,		"IQ_COUNTER1"},    {MSR_IQ_COUNTER2,		"IQ_COUNTER2"},    {MSR_IQ_COUNTER3,		"IQ_COUNTER3"},    {MSR_IQ_COUNTER4,		"IQ_COUNTER4"},