?? dsmlib.c
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/* dsmLib.c - i80x86 disassembler *//* Copyright 1984-2002 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01k,27mar02,hdn fixed the CALL/JMP ptr16:16/32 offset size (spr 73624)01j,30aug01,hdn added SIMD, sysenter/exit support. always print the disassembled address on 8 digits with 0x.01i,06may98,fle added P5 and P6 related instructions and facilities01h,14nov94,hdn changed D->DISR, W->WFUL, S->SEXT, P->POP, A->AX, I->IMM.01g,29may94,hdn removed I80486.01f,31aug93,hdn changed a type of 1st parameter, from char to UCHAR.01e,02aug93,hdn fixed a case that has mod=0,rm=5,disp32 operand.01d,01jun93,hdn updated to 5.1 - changed functions to ansi style - fixed #else and #endif - changed VOID to void - changed copyright notice01c,18mar93,hdn supported 486 instructions.01b,05nov92,hdn supported "16 bit operand","rep","repne","shift by 1". fixed a bug that is about "empty index".01a,23jun92,hdn written. *//*This library contains everything necessary to print i80x86 object code inassembly language format. The programming interface is via dsmInst(), which prints a single disassembledinstruction, and dsmNbytes(), which reports the size of an instruction.To disassemble from the shell, use l(), which calls thislibrary to do the actual work. See dbgLib for details.INCLUDE FILE: dsmLib.hSEE ALSO: dbgLib*/#include "vxWorks.h"#include "dsmLib.h"#include "symLib.h"#include "string.h"#include "stdio.h"#include "errnoLib.h"/* * This table is ordered by the number of bits in an instruction's * two word mask, beginning with the greatest number of bits in masks. * This scheme is used for avoiding conflicts between instructions * when matching bit patterns. The instruction ops are arranged * sequentially within each group of instructions for a particular * mask so that uniqueness can be easily spotted. *//* globals */LOCAL INST inst [] = { /* OP3 instructions */ {"ADDSS", itAddss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x58, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"CMPSS", itCmpss, OP3|MODRM|I8,XMMREG|XMMRM, 0xf3, 0x0f, 0xc2, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"CVTSI2SS", itCvtsi2ss, OP3|MODRM|REGRM,XMMREG, 0xf3, 0x0f, 0x2a, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"CVTSS2SI", itCvtss2si, OP3|MODRM|REG,XMMRM, 0xf3, 0x0f, 0x2d, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"CVTTSS2SI", itCvttss2si, OP3|MODRM|REG,XMMRM, 0xf3, 0x0f, 0x2c, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"DIVSS", itDivss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x5e, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"MAXSS", itMaxss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x5f, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"MINSS", itMinss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x5d, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"MOVSS", itMovss, OP3|MODRM|DISR,XMMREG|XMMRM, 0xf3, 0x0f, 0x10, /* opcode */ 0xff, 0xff, 0xfe}, /* mask */ {"MULSS", itMulss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x59, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"RCPSS", itRcpss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x53, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"RSQRTSS", itRsqrtss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x52, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"SQRTSS", itSqrtss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x51, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"SUBSS", itSubss, OP3|MODRM,XMMREG|XMMRM, 0xf3, 0x0f, 0x5c, /* opcode */ 0xff, 0xff, 0xff}, /* mask */ {"SFENCE", itSfence, OP3,0, 0x0f, 0xae, 0xc0, /* opcode */ 0xff, 0xff, 0xc0}, /* mask */ /* OP2 instructions extended by bits 3,4,5 of MODRM */ {"BT", itBtI, OP2|MODRM|I8,0, 0x0f, 0xba, 0x20, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"BTC", itBtcI, OP2|MODRM|I8,0, 0x0f, 0xba, 0x38, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"BTR", itBtrI, OP2|MODRM|I8,0, 0x0f, 0xba, 0x30, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"BTS", itBtsI, OP2|MODRM|I8,0, 0x0f, 0xba, 0x28, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LGDT", itLgdt, OP2|MODRM,0, 0x0f, 0x01, 0x10, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LIDT", itLidt, OP2|MODRM,0, 0x0f, 0x01, 0x18, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LLDT", itLldt, OP2|MODRM,0, 0x0f, 0x00, 0x10, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LMSW", itLmsw, OP2|MODRM,0, 0x0f, 0x01, 0x30, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LTR", itLtr, OP2|MODRM,0, 0x0f, 0x00, 0x08, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"SGDT", itSgdt, OP2|MODRM,0, 0x0f, 0x01, 0x00, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"SIDT", itSidt, OP2|MODRM,0, 0x0f, 0x01, 0x08, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"SLDT", itSldt, OP2|MODRM,0, 0x0f, 0x00, 0x00, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"SMSW", itSmsw, OP2|MODRM,0, 0x0f, 0x01, 0x20, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"STR", itStr, OP2|MODRM,0, 0x0f, 0x00, 0x08, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"VERR", itVerr, OP2|MODRM,0, 0x0f, 0x00, 0x20, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"VERW", itVerw, OP2|MODRM,0, 0x0f, 0x00, 0x28, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"FXRSTOR", itFxrstor, OP2|MODRM,0, 0x0f, 0xae, 0x08, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"FXSAVE", itFxsave, OP2|MODRM,0, 0x0f, 0xae, 0x00, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"LDMXCSR", itLdmxcsr, OP2|MODRM,0, 0x0f, 0xae, 0x10, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"STMXCSR", itStmxcsr, OP2|MODRM,0, 0x0f, 0xae, 0x18, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"PREFETCHT0", itPrefetcht0, OP2|MODRM,0, 0x0f, 0x18, 0x08, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"PREFETCHT1", itPrefetcht1, OP2|MODRM,0, 0x0f, 0x18, 0x10, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"PREFETCHT2", itPrefetcht2, OP2|MODRM,0, 0x0f, 0x18, 0x18, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"PREFETCHNTA", itPrefetchnta, OP2|MODRM,0, 0x0f, 0x18, 0x00, /* opcode */ 0xff, 0xff, 0x38}, /* mask */ {"MOVHLPS", itMovhlps, OP2|MODRM,XMMREG|XMMRM, 0x0f, 0x12, 0xc0, /* opcode */ 0xff, 0xff, 0xc0}, /* mask */ {"MOVLHPS", itMovlhps, OP2|MODRM,XMMREG|XMMRM, 0x0f, 0x16, 0xc0, /* opcode */ 0xff, 0xff, 0xc0}, /* mask */ /* OP2 instructions */ {"AAD", itAad, OP2,0, 0xd5, 0x0a, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"AAM", itAam, OP2,0, 0xd4, 0x0a, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BSF", itBsf, OP2|MODRM|REG,0, 0x0f, 0xbc, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BSR", itBsr, OP2|MODRM|REG,0, 0x0f, 0xbd, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BT", itBtR, OP2|MODRM|REG,0, 0x0f, 0xa3, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BTC", itBtcR, OP2|MODRM|REG,0, 0x0f, 0xbb, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BTR", itBtrR, OP2|MODRM|REG,0, 0x0f, 0xb3, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"BTS", itBtsR, OP2|MODRM|REG,0, 0x0f, 0xab, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"CLTS", itClts, OP2,0, 0x0f, 0x06, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"CMPXCHG8B", itCmpxchg8b, OP2|MODRM,0, 0x0f, 0xc7, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"CPUID", itCpuid, OP2,0, 0x0f, 0xa2, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"EMMS", itEmms, OP2,0, 0x0f, 0x77, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"F2XM1", itF2xm1, OP2,0, ESC|0x01, 0xf0, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FABS", itFabs, OP2,0, ESC|0x01, 0xe1, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FCHS", itFchs, OP2,0, ESC|0x01, 0xe0, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FCLEX", itFclex, OP2,0, ESC|0x03, 0xe2, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FCOMPP", itFcompp, OP2,0, ESC|0x06, 0xd9, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FCOS", itFcos, OP2,0, ESC|0x01, 0xff, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FDECSTP", itFdecstp, OP2,0, ESC|0x01, 0xf6, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FINCSTP", itFincstp, OP2,0, ESC|0x01, 0xf7, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FINIT", itFinit, OP2,0, ESC|0x03, 0xe3, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDZ", itFldZ, OP2,0, ESC|0x01, 0xee, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLD1", itFld1, OP2,0, ESC|0x01, 0xe8, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDPI", itFldPI, OP2,0, ESC|0x01, 0xeb, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDL2T", itFldL2T, OP2,0, ESC|0x01, 0xe9, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDL2E", itFldL2E, OP2,0, ESC|0x01, 0xea, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDLG2", itFldLG2, OP2,0, ESC|0x01, 0xec, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FLDLN2", itFldLN2, OP2,0, ESC|0x01, 0xed, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FNOP", itFnop, OP2,0, ESC|0x01, 0xd0, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FPATAN", itFpatan, OP2,0, ESC|0x01, 0xf3, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FPREM", itFprem, OP2,0, ESC|0x01, 0xf8, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FPREM1", itFprem1, OP2,0, ESC|0x01, 0xf5, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FPTAN", itFptan, OP2,0, ESC|0x01, 0xf2, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FRNDINT", itFrndint, OP2,0, ESC|0x01, 0xfc, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FSCALE", itFscale, OP2,0, ESC|0x01, 0xfd, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FSIN", itFsin, OP2,0, ESC|0x01, 0xfe, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FSINCOS", itFsincos, OP2,0, ESC|0x01, 0xfb, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FSQRT", itFsqrt, OP2,0, ESC|0x01, 0xfa, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FSTSW", itFstswA, OP2|AX,0, ESC|0x07, 0xe0, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FTST", itFtst, OP2,0, ESC|0x01, 0xe4, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FUCOMPP", itFucompp, OP2,0, ESC|0x02, 0xe9, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FXAM", itFxam, OP2,0, ESC|0x01, 0xe5, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FXTRACT", itFxtract, OP2,0, ESC|0x01, 0xf4, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FYL2X", itFyl2x, OP2,0, ESC|0x01, 0xf1, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"FYL2XP1", itFyl2xp1, OP2,0, ESC|0x01, 0xf9, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"IMUL", itImulRwiRM, OP2|MODRM|REG,0, 0x0f, 0xaf, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"INVD", itInvd, OP2,0, 0x0f, 0x08, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"INVLPG", itInvlpg, OP2|MODRM,0, 0x0f, 0x01, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"LAR", itLar, OP2|MODRM|REG,0, 0x0f, 0x02, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"LFS", itLfs, OP2|MODRM|REG,0, 0x0f, 0xb4, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"LGS", itLgs, OP2|MODRM|REG,0, 0x0f, 0xb5, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"LSL", itLsl, OP2|MODRM|REG,0, 0x0f, 0x03, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ {"LSS", itLss, OP2|MODRM|REG,0, 0x0f, 0xb2, 0x00, /* opcode */ 0xff, 0xff, 0x00}, /* mask */ /* * MOV Changes * see mask byte 2 changes on next entry. * This change is only done on entries that are extact, * with exception to opcode byte 2 bit 2 * * {"MOV", itMovC, OP2|DISR|EEE|MODRM,0, * 0x0f, 0x22, 0x00, * 0xff, 0xff, 0x00}, */ {"MOV", itMovC, OP2|DISR|EEE|MODRM,0, 0x0f, 0x20, 0x00, /* opcode */ 0xff, 0xfd, 0x00}, /* mask */ {"MOV", itMovD, OP2|DISR|EEE|MODRM,0, 0x0f, 0x21, 0x00, /* opcode */ 0xff, 0xfd, 0x00}, /* mask */ {"MOV", itMovT, OP2|DISR|EEE|MODRM,0, 0x0f, 0x24, 0x00, /* opcode */ 0xff, 0xfd, 0x00}, /* mask */?? 快捷鍵說明
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